M30879FLFP#U3 Renesas Electronics America, M30879FLFP#U3 Datasheet - Page 89

• Manufacturer Part Number: M30879FLFP#U3
• Description: IC M32C/87 MCU FLASH 100QFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLFP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-QFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

R
R
e
E
v
[src/dest Classified by Format]
G format*
Q format*
S format
J
Chapter 3
*3 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-, R1L/
*4 If you specify (.B) for the size specifier (.size), you cannot choose A0 and/or A1 for
*5 Indirect instruction addressing [dest] can be used in all addressing except R0L/R0/R2R0, R0H/R2/-,
*6 You can only specify (.B) or (.W) for the size specifier (.size).
*7 The range of values is -8 < #IMM4 < +7.
*8 Indirect instruction addressing [src] and [dest] can be used in all addressing except R0L/R0, and #IMM.
*9 You can only specify (.B) or (.W) for the size specifier (.size).
1 .
0
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM4/#IMM8/#IMM16/#IMM32
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
#IMM4*
R0L/R0
#IMM8/#IMM16
R0L/R0
#IMM
9
0 .
B
0
R1/R3R1, R1H/R3/-, and #IMM.
taneously.
R3R1, and R1H/R3/-.
0
3
1
2
9
0
7
0 -
0
*8*9
/#IMM8/#IMM16/#IMM32
3
5
6
1
*
4
0 .
6
0
0
5
3 .
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
dsp:8[SB]
dsp:8[SB]
Functions
1
p
a
g
e
src
src
src
4
71
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
R0H/R2/-
R1H/R3/-
dsp:8[FB]
dsp:8[FB]
f o
3
3
5
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
abs16
abs16
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0*
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
R0L/R0/R2R0
R1L/R1/R3R1
A0/A0/A0
dsp:8[A0]
dsp:16[A0]
dsp:24[A0]
R0L/R0
R0L/R0
4
A1/A1/A1*
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
A1/A1/A1
dsp:8[A1]
dsp:16[A1]
dsp:24[A1]
dsp:8[SB]
dsp:8[SB]
dest
dest
dest
4
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
R0H/R2/-
R1H/R3/-
[A0]
dsp:8[SB]
dsp:16[SB]
abs24
dsp:8[FB]
dsp:8[FB]
src
and
3.2 Functions
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
[A1]
dsp:8[FB]
dsp:16[FB]
abs16
dest
abs16
abs16
R1L/R1/
simul-