M30879FLGP#U3 Renesas Electronics America, M30879FLGP#U3 Datasheet - Page 26

• Manufacturer Part Number: M30879FLGP#U3
• Description: IC M32C/87 MCU FLASH 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M30879FLGP#U3

• Core Size: 16/32-Bit
• Program Memory Size: 1MB (1M x 8)
• Core Processor: M32C/80
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 26x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Controller Family/series: M32C
• No. Of I/o's: 85
• Ram Memory Size: 48KB
• Cpu Speed: 32MHz
• No. Of Timers: 2
• Digital Ic Case Style: LQFP
• Embedded Interface Type: CAN, I2C, UART
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 24 of 85
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.8.1
2.1.8.2
2.1.8.3
2.1.8.4
2.1.8.5
2.1.8.6
R0, R1, R2, and R3 are 16-bit registers for transfer, arithmetic and logic operations. R0 and R1 can be split into
high-order (R0H/R1H) and low-order bits (R0L/R1L) to be used separately as 8-bit data registers.
R0 can be combined with R2 and used as a 32-bit data register (R2R0). The same applies to R3R1.
A0 and A1 are 24-bit registers used for A0-/A1-indirect addressing, A0-/A1-relative addressing, transfer,
arithmetic and logic operations.
SB is a 24-bit register used for SB-relative addressing.
FB is a 24-bit register used for FB-relative addressing.
The stack pointers (SP), USP and ISP, are 24 bits wide each. The U flag is used to switch between USP and ISP.
Refer to 2.1.8 Flag Register (FLG) for details on the U flag. Set USP and ISP to even addresses to execute an
interrupt sequence efficiently.
INTB is a 24-bit register indicating the starting address of a relocatable interrupt vector table.
PC is 24 bits wide and indicates the address of the next instruction to be executed.
FLG is a 16-bit register indicating the CPU state.
General Registers
The C flag indicates whether or not carry or borrow has been generated after executing an instruction.
The D flag is for debugging only. Set it to 0.
The Z flag becomes 1 when an arithmetic operation results in 0; otherwise becomes 0.
The S flag becomes 1 when an arithmetic operation results in a negative value; otherwise becomes 0.
Register bank 0 is selected when the B flag is set to 0. Register bank 1 is selected when this flag is set to 1.
The O flag becomes 1 when an arithmetic operation results in an overflow; otherwise becomes 0.
Data Registers (R0, R1, R2, and R3)
Address Registers (A0 and A1)
Static Base Register (SB)
Frame Base Register (FB)
User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Interrupt Table Register (INTB)
Program Counter (PC)
Flag Register (FLG)
Carry Flag (C)
Debug Flag (D)
Zero Flag (Z)
Sign Flag (S)
Register Bank Select Flag (B)
Overflow Flag (O)
2. Central Processing Unit (CPU)