M30622F8PGP#U7C Renesas Electronics America, M30622F8PGP#U7C Datasheet - Page 274
![IC M16C MCU FLASH 64K 100LQFP](/photos/12/29/122905/m30622f8pgp_u7c_sml.jpg)
M30622F8PGP#U7C
Manufacturer Part Number
M30622F8PGP#U7C
Description
IC M16C MCU FLASH 64K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30622F8PGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30622F8PGP#U7CM30622F8PGP#D3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Part Number:
M30622F8PGP#U7CM30622F8PGP#D5C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 5.3.2 Stack status before and after an interrupt request is acknowledged
Chapter 5
Table 5.3.2 Relationship between Interrupts without Interrupt Priority Levels and IPL
Address
5.3.2 Changes of IPL When Interrupt Request Acknowledged
5.3.3 Saving Registers
Stack status before interrupt request is acknowledged
Interrupt sources without interrupt priority levels
Watchdog timer, NMI
Reset
Other
When an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is
set to the processor interrupt priority level (IPL).
If an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in
Table 5.3.2 is set to the IPL.
In an interrupt sequence, only the contents of the flag register (FLG) and program counter (PC) are
saved to the stack area.
The order in which these contents are saved is as follows: First, the 4 high-order bits of the program
counter and 4 high-order bits and 8 low-order bits of the FLG register for a total of 16 bits are saved to
the stack area. Next, the 16 low-order bits of the program counter are saved. Figure 5.3.2 shows the
stack status before an interrupt request is acknowledged and the stack status after an interrupt request
is acknowledged.
If there are any other registers you want to be saved, save them in software at the beginning of the
interrupt routine. The PUSHM instruction allows you to save all registers except the stack pointer (SP)
by a single instruction.
m–4
m–3
m–2
m–1
m
m+1
MSB
Content of
previous stack
Content of
previous stack
Stack area
Interrupt
_______
LSB
[SP]
Stack pointer
value before
interrupt occurs
256
Address
Stack status after interrupt request is acknowledged
Value that is set to IPL
m–4
m–3
m–2
m–1
m
m+1
MSB
Not changed
Flag register
Content of
previous stack
Content of
previous stack
Program counter
Program counter
Flag register
(FLG
Stack area
7
0
(FLG
H
)
(PC
(PC
L
M
L
)
)
)
Program counter
(PC
5.3 Interrupt Sequence
H
)
LSB
[SP]
New stack
pointer value
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