MC908AZ60AMFUE Freescale Semiconductor, MC908AZ60AMFUE Datasheet - Page 254

• Manufacturer Part Number: MC908AZ60AMFUE
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AMFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Operating Supply Voltage: 5 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Package: 64PQFP
• Family Name: HC08
• Maximum Speed: 8.4 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Input/Output Ports
22.4 Port C
Port C is an 6-bit general-purpose bidirectional I/O port. Note that PTC5 is only available on 64-pin
package options.
22.4.1 Port C Data Register
The port C data register contains a data latch for each of the six port C pins.
PTC[5:0] — Port C Data Bits
MCLK — System Clock Bit
22.4.2 Data Direction Register C
Data direction register C determines whether each port C pin is an input or an output. Writing a logic 1 to
a DDRC bit enables the output buffer for the corresponding port C pin; a logic 0 disables the output buffer.
MCLKEN — MCLK Enable Bit
254
These read/write bits are software-programmable. Data direction of each port C pin is under the control
of the corresponding bit in data direction register C. Reset has no effect on port C data (5:0).
The system clock is driven out of PTC2 when enabled by MCLKEN bit in PTCDDR7.
This read/write bit enables MCLK to be an output signal on PTC2. If MCLK is enabled, DDRC2 has no
effect. Reset clears this bit.
1 = MCLK output enabled
0 = MCLK output disabled
Alternative
Functions:
Address:
Address:
Reset:
Reset:
Read:
Read:
Write:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
MCLKEN
$0002
$0006
Bit 7
Bit 7
R
R
R
0
0
Figure 22-9. Data Direction Register C (DDRC)
= Reserved
= Reserved
Figure 22-8. Port C Data Register (PTC)
R
R
6
0
6
0
0
DDRC5
PTC5
5
5
0
DDRC4
Unaffected by Reset
PTC4
4
4
0
DDRC3
PTC3
3
3
0
DDRC2
MCLK
PTC2
2
2
0
DDRC1
PTC1
1
1
0
Freescale Semiconductor
DDRC0
PTC0
Bit 0
Bit 0
0