MC908AZ60AMFUE Freescale Semiconductor, MC908AZ60AMFUE Datasheet - Page 125

• Manufacturer Part Number: MC908AZ60AMFUE
• Description: IC MCU FLASH 8.4MHZ 60K 64QFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908AZ60AMFUE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8.4MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 52
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 15x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-QFP
• Processor Series: HC08AZ
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8.4 MHz
• Number Of Programmable I/os: 52
• Number Of Timers: 8
• Operating Supply Voltage: 5 V to 5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, M68CBL05CE, ZK-HC08AX-A, M68EM08AS/AZ60AE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 15 Channel
• Package: 64PQFP
• Family Name: HC08
• Maximum Speed: 8.4 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ILOP — Illegal Opcode Reset Bit
ILAD — Illegal Address Reset Bit (opcode fetches only)
LVI — Low-Voltage Inhibit Reset Bit
9.7.3 SIM Break Flag Control Register
The SIM break control register contains a bit that enables software to clear status bits while the MCU is
in a break state.
BCFE — Break Clear Flag Enable Bit
Freescale Semiconductor
This read/write bit enables software to clear status bits by accessing status registers while the MCU is
in a break state. To clear status bits during the break state, the BCFE bit must be set.
1 = Last reset caused by an illegal opcode
0 = POR or read of SRSR
1 = Last reset caused by an opcode fetch from an illegal address
0 = POR or read of SRSR
1 = Last reset was caused by the LVI circuit
0 = POR or read of SRSR
1 = Status bits clearable during break
0 = Status bits not clearable during break
Address:
Reset:
Read:
Write:
MC68HC908AZ60A • MC68HC908AS60A • MC68HC908AS60E Data Sheet, Rev. 6
$FE03
Figure 9-19. SIM Break Flag Control Register (SBFCR)
BCFE
Bit 7
R
0
R
6
= Reserved
R
5
R
4
R
3
R
2
R
1
0
Bit 0
R
SIM Registers
125