C8051F349-GM Silicon Laboratories Inc, C8051F349-GM Datasheet - Page 108
![IC 8051 MCU 32K FLASH MEM 32-QFN](/photos/12/27/122747/c8051f349-gm_sml.jpg)
C8051F349-GM
Manufacturer Part Number
C8051F349-GM
Description
IC 8051 MCU 32K FLASH MEM 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F34xr
Datasheet
1.C8051F349-GQ.pdf
(276 pages)
Specifications of C8051F349-GM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Interface Type
I2C, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.25 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
KSK-SL-F34X, KSK-SL-TOOLSTICK, PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F340DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1748 - ADAPTER TOOLSTICK FOR C8051F34X
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1349-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F349-GM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F340/1/2/3/4/5/6/7/8/9/A/B/C/D
12.1.3. Flash Write Procedure
Bytes in Flash memory can be written one byte at a time, or in groups of two. The FLBWE bit in register
PFE0CN (SFR Definition 10.1) controls whether a single byte or a block of two bytes is written to Flash
during a write operation. When FLBWE is cleared to ‘0’, the Flash will be written one byte at a time. When
FLBWE is set to ‘1’, the Flash will be written in two-byte blocks. Block writes are performed in the same
amount of time as single-byte writes, which can save time when storing large amounts of data to Flash
memory.During a single-byte write to Flash, bytes are written individually, and a Flash write will be per-
formed after each MOVX write instruction. The recommended procedure for writing Flash in single bytes is:
Steps 5-7 must be repeated for each byte to be written.
For block Flash writes, the Flash write procedure is only performed after the last byte of each block is writ-
ten with the MOVX write instruction. A Flash write block is two bytes long, from even addresses to odd
addresses. Writes must be performed sequentially (i.e. addresses ending in 0b and 1b must be written in
order). The Flash write will be performed following the MOVX write that targets the address ending in 1b. If
a byte in the block does not need to be updated in Flash, it should be written to 0xFF. The recommended
procedure for writing Flash in blocks is:
Steps 5–10 must be repeated for each block to be written.
108
Step 1. Disable interrupts.
Step 2. Clear the FLBWE bit (register PFE0CN) to select single-byte write mode.
Step 3. Set the PSWE bit (register PSCTL).
Step 4. Clear the PSEE bit (register PSCTL).
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write a single data byte to the desired location within the
Step 8. Clear the PSWE bit.
Step 9. Re-enable interrupts.
Step 1. Disable interrupts.
Step 2. Set the FLBWE bit (register PFE0CN) to select block write mode.
Step 3. Set the PSWE bit (register PSCTL).
Step 4. Clear the PSEE bit (register PSCTL).
Step 5. Write the first key code to FLKEY: 0xA5.
Step 6. Write the second key code to FLKEY: 0xF1.
Step 7. Using the MOVX instruction, write the first data byte to the even block location (ending in
Step 8. Write the first key code to FLKEY: 0xA5.
Step 9. Write the second key code to FLKEY: 0xF1.
Step 10. Using the MOVX instruction, write the second data byte to the odd block location (ending
Step 11. Clear the PSWE bit.
Step 12. Re-enable interrupts.
512-byte sector.
0b).
in 1b).
Rev. 1.3
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