C8051F707-GM Silicon Laboratories Inc, C8051F707-GM Datasheet - Page 40

IC 8051 MCU 16K FLASH 48-QFN

C8051F707-GM

Manufacturer Part Number
C8051F707-GM
Description
IC 8051 MCU 16K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Datasheets

Specifications of C8051F707-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1606-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F707-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
C8051F70x/71x
40
Notes:
General
Solder Mask Design
Stencil Design
Card Assembly
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This land pattern design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body
pad is to be 60 m minimum, all the way around the pad.
solder paste release.
Components.
Dimension
C1
C2
X1
Y1
E
Table 5.2. TQFP-48 PCB Land Pattern Dimensions
Figure 5.2. TQFP-48 PCB Land Pattern
Rev. 1.0
8.30
8.30
0.20
1.40
Min
0.50 BSC
Max
8.40
8.40
0.30
1.50

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