C8051F707-GM Silicon Laboratories Inc, C8051F707-GM Datasheet - Page 167

IC 8051 MCU 16K FLASH 48-QFN

C8051F707-GM

Manufacturer Part Number
C8051F707-GM
Description
IC 8051 MCU 16K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F70xr
Datasheets

Specifications of C8051F707-GM

Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Cap Sense, POR, PWM, WDT
Number Of I /o
39
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-QFN
Processor Series
C8051F7x
Core
8051
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
I2C, SMBus, SPI, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
39
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F700DK
Minimum Operating Temperature
- 40 C
For Use With
336-1635 - DEV KIT FOR C8051F700
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
336-1606-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F707-GM
Manufacturer:
Silicon Laboratories Inc
Quantity:
135
25.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
25.6. Watchdog Timer Reset
The programmable Watchdog Timer (WDT) can be used to prevent software from running out of control
during a system malfunction. The WDT function can be enabled or disabled by software as described in
Section “26. Watchdog Timer” on page 169. If a system malfunction prevents user software from updating
the WDT, a reset is generated and the WDTRSF bit (RSTSRC.3) is set to 1. The state of the RST pin is
unaffected by this reset.
25.7. Flash Error Reset
If a Flash read/write/erase or program read targets an illegal address, a system reset is generated. This
may occur due to any of the following:
The FERROR bit (RSTSRC.6) is set following a Flash error reset. The state of the RST pin is unaffected by
this reset.
25.8. Software Reset
Software may force a reset by writing a 1 to the SWRSF bit (RSTSRC.4). The SWRSF bit will read 1 fol-
lowing a software forced reset. The state of the RST pin is unaffected by this reset.




write operation targets an address above address 0x3DFF.
above address 0x3DFF.
address above 0x3DFF.
Options” on page 149
A Flash write or erase is attempted above user code space. This occurs when PSWE is set to 1 and a MOVX
A Flash read is attempted above user code space. This occurs when a MOVC operation targets an address
A Program read is attempted above user code space. This occurs when user code attempts to branch to an
A Flash read, write or erase attempt is restricted due to a Flash security setting (see
).
Rev. 1.0
C8051F70x/71x
Section “22.3. Security
167

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