C8051F553-IM Silicon Laboratories Inc, C8051F553-IM Datasheet - Page 44
C8051F553-IM
Manufacturer Part Number
C8051F553-IM
Description
IC 8051 MCU 32K FLASH 24-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F55xr
Specifications of C8051F553-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
18
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 18x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
18
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1686-5
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C8051F55x/56x/57x
Table 5.9. ADC0 Electrical Characteristics
VDDA
44
DC Accuracy
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Full Scale Error
Offset Temperature Coefficient
Dynamic performance (10 kHz sine-wave single-ended input, 1 dB below Full Scale, 200 ksps)
Signal-to-Noise Plus Distortion
Total Harmonic Distortion
Spurious-Free Dynamic Range
Conversion Rate
SAR Conversion Clock
Conversion Time in SAR Clocks
Track/Hold Acquisition Time
Throughput Rate
Analog Inputs
ADC Input Voltage Range
Absolute Pin Voltage with respect
to GND
Sampling Capacitance
Input Multiplexer Impedance
Power Specifications
Power Supply Current
(VDDA supplied to ADC0)
Burst Mode (Idle)
Power-On Time
Power Supply Rejection
Notes:
1. Represents one standard deviation from the mean. Offset and full-scale error can be removed through
2. An additional 2 FCLK cycles are required to start and complete a conversion
3. Additional tracking time may be required depending on the output impedance connected to the ADC input.
4. An increase in tracking time will decrease the ADC throughput.
5. See Section “
= 1.8 to 2.75 V, –40 to +125 °C, VREF = 1.5 V (REFSL=0) unless otherwise specified.
calibration.
See Section “
Parameter
1
4
6.2.1. Settling Time Requirements
6.3. Selectable Gain
5
3
2
Guaranteed Monotonic
Up to the 5th harmonic;
VDDA > 2.0 V
VDDA < 2.0 V
VDDA > 2.0 V
gain = 1.0 (default)
gain = n
Operating Mode, 200 ksps
” on page
Conditions
53
Rev. 1.1
for more information about the setting the gain.
” on page
52
.
Min
–10
–20
1.5
3.5
63
13
—
—
—
—
—
—
—
—
—
—
—
—
0
0
0
5
1100
1100
±0.5
±0.5
Typ
–60
-82
3.0
5.7
7.7
65
80
31
—
—
—
—
—
—
—
—
3
12
VREF / n
VREF
1500
1500
Max
200
V
3.6
±3
±1
10
20
—
—
—
—
—
—
—
—
—
—
—
IO
ppm/°C
clocks
Units
mV/V
MHz
ksps
LSB
LSB
LSB
LSB
bits
k
µA
µA
dB
dB
dB
pF
µs
µs
V
V
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