C8051F553-IM Silicon Laboratories Inc, C8051F553-IM Datasheet - Page 220

• Manufacturer Part Number: C8051F553-IM
• Description: IC 8051 MCU 32K FLASH 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F55xr

Specifications of C8051F553-IM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 24-QFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 18
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 18x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1686-5

C8051F55x/56x/57x
The SMBCS1–0 bits select the SMBus clock source, which is used only when operating as a master or
when the Free Timeout detection is enabled. When operating as a master, overflows from the selected
source determine the absolute minimum SCL low and high times as defined in Equation 22.1. Note that the
selected clock source may be shared by other peripherals so long as the timer is left running at all times.
For example, Timer 1 overflows may generate the SMBus and UART baud rates simultaneously. Timer
configuration is covered in Section “25. Timers” on page 255.
The selected clock source should be configured to establish the minimum SCL High and Low times as per
Equation 22.1. When the interface is operating as a master (and SCL is not driven or extended by any
other devices on the bus), the typical SMBus bit rate is approximated by Equation 22.2.
Figure 22.4 shows the typical SCL generation described by Equation 22.2. Notice that T
twice as large as T
extended low by slower slave devices, or driven low by contending master devices). The bit rate when
operating as a master will never exceed the limits defined by equation Equation 22.1.
220
Timer Source
Overflows
SCL
LOW
T
Equation 22.1. Minimum SCL High and Low Times
. The actual SCL output may vary due to other devices on the bus (SCL may be
Low
SMBCS1
0
0
1
1
T
Figure 22.4. Typical SMBus SCL Generation
HighMin
Table 22.1. SMBus Clock Source Selection
Equation 22.2. Typical SMBus Bit Rate
BitRate
SMBCS0
0
1
0
1
=
T
High
T
LowMin
=
f
-------------------------------------------------
ClockSourceOverflow
SMBus Clock Source
Timer 0 Overflow
Timer 1 Overflow
Timer 2 High Byte Overflow
Timer 2 Low Byte Overflow
Rev. 1.1
=
-------------------------------------------------
f
ClockSourceOverflow
3
1
SCL High Timeout
HIGH
is typically