MC908JL16CPE Freescale Semiconductor, MC908JL16CPE Datasheet - Page 116

• Manufacturer Part Number: MC908JL16CPE
• Description: IC MCU 16K FLASH 8MHZ 28-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JL16CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI
• Peripherals: LED, LVD, POR, PWM
• Number Of I /o: 23
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-DIP (0.600", 15.24mm)
• Controller Family/series: HC08
• No. Of I/o's: 23
• Ram Memory Size: 512Byte
• Cpu Speed: 8MHz
• No. Of Timers: 2
• Embedded Interface Type: I2C, SCI
• Rohs Compliant: Yes
• Processor Series: HC08JL
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 23
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908JL16E, M68CBL05CE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: DEMO908JL16E - BOARD DEMO FOR MC908JL16
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Multi-Master IIC Interface (MMIIC)
The MMIIC module will respond to the calling address:
or the general calling address:
or the calling address:
8.8.2 Multi-Master IIC Control Register (MMCR)
MMEN — Multi-Master IIC Enable
MMIEN — Multi-Master IIC Interrupt Enable
MMTXAK — Transmit Acknowledge Enable
REPSEN — Repeated Start Enable
116
This bit is set to enable the Multi-master IIC module. When MMEN = 0, module is disabled and all flags
will restore to its power-on default states. Reset clears this bit.
When this bit is set, the MMTXIF, MMRXIF, MMALIF, and MMNAKIF flags are enabled to generate an
interrupt request to the CPU. When MMIEN is cleared, the these flags are prevented from generating
an interrupt request. Reset clears this bit.
This bit is set to disable the MMIIC from sending out an acknowledge signal to the bus at the 9th clock
bit after receiving 8 data bits. When MMTXAK is cleared, an acknowledge signal will be sent at the 9th
clock bit. Reset clears this bit.
This bit is set to enable repeated START signal to be generated when in master mode transfer
(MMAST = 1). The REPSEN bit is cleared by hardware after the completion of repeated START signal
or when the MMAST bit is cleared. Reset clears this bit.
1 = MMIIC module enabled
0 = MMIIC module disabled
1 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will generate interrupt request to CPU
0 = MMTXIF, MMRXIF, MMALIF, and/or MMNAKIF bit set will not generate interrupt request to CPU
1 = MMIIC does not send acknowledge signals at 9th clock bit
0 = MMIIC sends acknowledge signal at 9th clock bit
1 = Repeated START signal will be generated if MMAST bit is set
0 = No repeated START signal will be generated
Address: $0042
Bit 0 of the 8-bit calling address is the MMRW bit from the calling master.
Reset:
Read:
Write:
MMEN
Bit 7
Bit 7
Figure 8-5. Multi-Master IIC Control Register (MMCR)
0
1
0
0
= Unimplemented
MMIEN
0
6
1
0
6
0
MC68HC908JL16 Data Sheet, Rev. 1.1
5
0
0
0
5
0
0
NOTE
4
1
0
1
4
0
0
MMTXAK
3
0
0
1
3
0
REPSEN
2
1
0
0
2
0
Bit 1
0
0
0
1
0
0
Freescale Semiconductor
Bit 0
0
0