C8051F546-IM Silicon Laboratories Inc, C8051F546-IM Datasheet - Page 167

• Manufacturer Part Number: C8051F546-IM
• Description: IC 8051 MCU 8K FLASH 24-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F54xr

Specifications of C8051F546-IM

• Program Memory Type: FLASH
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 24-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 18
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 18x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 18
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F540DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1672 - BOARD PROTOTYPE W/C8051F540336-1669 - KIT DEVELOPMENT FOR C8051F540
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1681-5

SFR Definition 18.23. P2SKIP: Port 2 Skip
SFR Address = 0xD6; SFR Page = 0x0F
SFR Definition 18.24. P3: Port 3
SFR Address = 0xB0; SFR Page = All Pages; Bit-Addressable
Note: P2.2-P2.7 are only available on the 32-pin packages.
Note: Port P3.0 is only available on the 32-pin packages.
Name
Reset
Name
Reset
Bit
7:0
Bit
7:1
Type
Type
0
Bit
Bit
Unused
P2SKIP[7:0]
Name
P3[0]
Name
R
7
0
7
1
Read = 0000000b; Write = Don’t Care.
Port 3 Data.
Sets the Port latch logic
value or reads the Port pin
logic state in Port cells con-
figured for digital I/O.
Port 2 Crossbar Skip Enable Bits.
These bits select Port 2 pins to be skipped by the Crossbar Decoder. Port pins
used for analog, special functions or GPIO should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
R
6
0
6
1
Description
R
5
0
5
1
Rev. 1.1
0: Set output latch to logic
LOW.
1: Set output latch to logic
HIGH.
R
4
0
4
1
P2SKIP[7:0]
R/W
Function
Write
R
3
0
3
1
R
2
0
2
1
0: P3.n Port pin is logic
LOW.
1: P3.n Port pin is logic
HIGH.
C8051F54x
R
1
0
1
1
Read
R/W
P3
0
0
0
1
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