C8051T602-GM Silicon Laboratories Inc, C8051T602-GM Datasheet - Page 75
![IC 8051 MCU 4K-EEPROM 11-QFN](/photos/12/25/122559/c8051t602-gm_sml.jpg)
C8051T602-GM
Manufacturer Part Number
C8051T602-GM
Description
IC 8051 MCU 4K-EEPROM 11-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T60xr
Datasheet
1.C8051T600EDB.pdf
(188 pages)
Specifications of C8051T602-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Program Memory Size
4KB (4K x 8)
Program Memory Type
OTP
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
11-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T600DK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
For Use With
336-1404 - KIT DEV FOR C8051T60X MCU'S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Other names
336-1654-5
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15.2. Data Memory
The C8051T600/1/2/3/4/5 devices include 256 bytes of RAM, and the C8051T606 devices include 128
bytes of RAM. This memory is mapped into the internal data memory space of the 8051 controller core.
The RAM memory organization of the C8051T600/1/2/3/4/5/6 device family is shown in Figure 15.2
15.2.1. Internal RAM
The 256 bytes of internal RAM on the C8051T600/1/2/3/4/5 are mapped into the data memory space from
0x00 through 0xFF. The 128 bytes of internal RAM on the C8051T606 are mapped into the data memory
space from 0x00 through 0x7F. The 128 bytes of data memory from 0x00 to 0x7F on all devices are used
for general purpose registers and scratch pad memory. Either direct or indirect addressing may be used to
access these 128 bytes of data memory. Locations 0x00 through 0x1F are addressable as four banks of
general purpose registers, each bank consisting of eight byte-wide registers. The next 16 bytes, locations
0x20 through 0x2F, may either be addressed as bytes or as 128 bit locations accessible with the direct
addressing mode.
The upper 128 bytes of data memory available on the C8051T600/1/2/3/4/5 are accessible only by indirect
addressing. This region occupies the same address space as the Special Function Registers (SFR) but is
physically separate from the SFR space. The addressing mode used by an instruction when accessing
locations above 0x7F determines whether the CPU accesses the upper 128 bytes of data memory space
or the SFRs. Instructions that use direct addressing will access the SFR space. Instructions using indirect
addressing above 0x7F access the upper 128 bytes of data memory. Figure 15.2 illustrates the data mem-
ory organization of the C8051T600/1/2/3/4/5/6.
0xFF
0x7F
0x2F
0x1F
0x80
0x30
0x20
0x00
Upper 128 Bytes RAM
(Indirect Addressing)
‘T600/1/2/3/4/5 Only
(Direct and Indirect
General Purpose
Figure 15.2. RAM Memory Map
Bit Addressable
Addressing)
Registers
Rev. 1.2
(Direct Addressing)
C8051T600/1/2/3/4/5/6
Special Function
Lower 128 Bytes RAM
(Direct and Indirect
Addressing)
Registers
75
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