CY8CLED16P01-48LFXI Cypress Semiconductor Corp, CY8CLED16P01-48LFXI Datasheet - Page 11

• Manufacturer Part Number: CY8CLED16P01-48LFXI
• Description: IC PLC PSOC CMOS LED 16CH 48VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: PowerPSoC® CY8CLEDr

Specifications of CY8CLED16P01-48LFXI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: LED, PLC, POR, PWM, WDT
• Number Of I /o: 44
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 4x14b; D/A 4x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

3.1 Programmable System Resources
Figure 3-2. Programmable System Resources
3.1.1 The Digital System
The digital system contains 16 digital PSoC blocks. Each block
is an 8-bit resource that can be used alone, or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals called
user module references. Digital peripheral configurations
include:
■
■
■
■
■
■
■
■
■
■
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also enable signal multiplexing and perform logic opera-
tions. This configurability frees your designs from the constraints
of a fixed peripheral controller.
Document Number: 001-49263 Rev. *E
PWMs (8 to 32 bit)
PWMs with Dead Band (8 to 32 bit)
Counters (8 to 32 bit)
Timers (8 to 32 bit)
UART 8 bit with selectable parity (up to four)
SPI master and slave (up to four each)
I
Resource)
Cyclical Redundancy Checker and Generator (8 to 32 bit)
IrDA (up to 4)
Pseudo Random Sequence Generators (8 to 32 bit)
2
Network Protocol
PLC Core
C slave and multi-master (one available as a System
Physical Layer
FSK Modem
Powerline
Powerline Communication Solution
Powerline Transceiver Packet
Embedded Application
PSoC Core
System Resources
MAC, Decimator, I2C,
Additional System
Digital and Analog
Programmable
SPI, UART etc.
Resources
Peripherals
Controller
Communication
PrISM, PWM etc.
HB LED
DALI, DMX512
Technology
Modulation
Additional
Interface
Figure 3-3. Digital System Block Diagram
8
8
Port 7
Port 6
GIO[7:0]
GIE[7:0]
DBB00
DBB10
DBB20
DBB30
Port 5
Digital PSoC Block Array
DIGITAL SYSTEM
To System Bus
DBB01
DBB11
DBB21
DBB31
Port 4
Global Digital
Interconnect
Row 0
Row 1
Row 2
Row 3
DCB02
DCB12
DCB22
DCB32
Port 3
CY8CLED16P01
Port 2
DCB03
DCB13
DCB23
DCB33
GOE[7:0]
To Analog
GOO[7:0]
System
4
4
4
4
4
4
4
4
Port 1
Page 11 of 46
Port 0
8
8
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