Z86E4412PSG Zilog, Z86E4412PSG Datasheet - Page 28

• Manufacturer Part Number: Z86E4412PSG
• Description: IC MICROCONTROLLER 16K 40-DIP
• Manufacturer: Zilog
• Series: Z8®r

Specifications of Z86E4412PSG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 12MHz
• Connectivity: EBI/EMI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 3.5 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.620", 15.75mm)
• Processor Series: Z86E4xx
• Core: Z8
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 3.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: Z86E4400ZDV, Z86E4400ZDP, Z86E4400ZDF, Z86E3400ZDV, Z86E3400ZDS, Z86E3400ZDP, Z86C4001ZDV
• Minimum Operating Temperature: 0 C
• For Use With: 309-1034 - ADAPTER 40-DIP ZIF TO 44-QFP309-1033 - ADAPTER 40-DIP TO 44-QFP309-1030 - ADAPTER 40-DIP TO 44-PLCC309-1029 - ADAPTER 40-DIP ZIF TO 44-PLCC
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-3980; Z86E4412PSG

PIN FUNCTIONS (Continued)
Z86E33/733/E34/E43/743/E44
CMOS Z8 OTP Microcontrollers
Port 1 (P17-P10). Port 1 is an 8-bit, bidirectional, CMOS-
compatible port with multiplexed Address (A7-A0) and
Data (D7-D0) ports. These eight I/O lines can be pro-
grammed as inputs or outputs or can be configured under
software control as an Address/Data port for interfacing
external memory. The input buffers are Schmitt-triggered
and the output buffers can be globally programmed as ei-
ther push-pull or open-drain. Low EMI output buffers can
be globally programmed by the software. Port 1 can be
placed under handshake control. In this configuration, Port
3, lines P33 and P34 are used as the handshake controls
28
Open-Drain
OEN
Out
In
Figure 19. Port 1 Configuration (
1.5
MCU
2.3V Hysteresis
P R E L I M I N A R Y
Port 2 (I/O)
Handshake Controls
/DAV1 and RDY1
R
(P33 and P34)
RDY1 and /DAV1 (Ready and Data Available). To inter-
face external memory, Port 1 must be programmed for the
multiplexed Address/Data mode. If more than 256 external
locations are required, Port 0 outputs the additional lines
(Figure 19).
Port 1 can be placed in the high-impedance state along
with Port 0, /AS, /DS, and R//W, allowing the
Z86E43/743/E44
cessor and DMA applications. In ROM mode, Port 1 is de-
fined as input after reset.
500 k
Z86E43/743/E44
to share common resources in multipro-
Only)
Auto Latch
PAD
DS97Z8X1500
Zilog