Z16F2810VH20EG Zilog, Z16F2810VH20EG Datasheet - Page 149

• Manufacturer Part Number: Z16F2810VH20EG
• Description: IC ZNEO MCU FLASH 128K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® ZNEOr

Specifications of Z16F2810VH20EG

• Core Processor: ZNEO
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 68-LCC (J-Lead)
• Data Bus Width: 16 bit
• Data Ram Size: 4 B
• Interface Type: ESPI, I2C, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• For Use With: 770-1003 - ISP 4PORT FOR ZILOG ZNEO MCU269-4537 - DEV KIT FOR Z16F ZNEO
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4691-5; Z16F2810VH20EG

Table 79. Current-Sense Sample and Hold Control Register (CSSHR0 and CSSHR1)
.
BITS
FIELD
RESET
R/W
ADDR
PS022008-0810
Bit Position
[7]
SHPOL
[6]
HEN
[5]
NHEN
[4]
LEN
[3]
NLEN
[2]
SHPWM2
[1]
SHPWM1
[0]
SHPWM0
SHPOL
R/W
7
0
Value (H)
activate the internal hold signal. Disabling the HEN, LEN, NHEN, and NLEN bits allows
software control of the input sample/hold by writing the SHPOL bit.
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
HEN
R/W
6
0
Description
Sample Hold Polarity
Hold when terms are active.
Hold when terms are not active.
High Side Active enable
Ignore Product of PWMH0, PWMH1, PWMH2 in sample/hold equation.
Hold when PWMH0, PWMH1, PWMH2 are all active.
High Side inactive enable
Ignore product of
Hold when are all active.
Low Side Active enable
Ignore product of PWML0, PWML1, PWML2 in sample/hold equation.
Hold when PWML0, PWML1, PWML2 are all active.
Low Side Inactive enable
Ignore product of
Hold when
PWM channel2 Sample/Hold Enable
Channel 2 terms are not used in sample/hold equation.
Channel 2 terms are used in sample/hold equation.
PWM channel1 sample/hold equation
Channel 1 terms are not used in sample/hold equation.
Channel 1 terms are used in sample/hold equation.
PWM channel0 sample/hold equation
Channel 0 terms are not used in sample/hold equation.
Channel 0 terms are used in sample/hold equation.
NHEN
R/W
PWML0
5
0
P R E L I M I N A R Y
FF_E38AH and FF_E38BH
PWMH0
PWML0
,
PWML1
LEN
R/W
4
0
,
,
PWML1
PWMH1
,
PWML2
NLEN
R/W
3
0
,
,
PWML2
PWMH2
are all active.
SHPWM2 SHPWM1 SHPWM0
R/W
in sample/hold equation.
2
0
in sample/hold equation.
Multi-Channel PWM Timer
Product Specification
ZNEO
R/W
1
0
Z16F Series
R/W
0
0
134