ST7FLITE02Y0B6 STMicroelectronics, ST7FLITE02Y0B6 Datasheet - Page 48

• Manufacturer Part Number: ST7FLITE02Y0B6
• Description: MCU 8BIT 1.5K FLASH 16DIP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FLITE02Y0B6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 13
• Program Memory Size: 1.5KB (1.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 16-DIP (0.300", 7.62mm)
• Processor Series: ST7FLITE0x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ST7FLIT0-IND/USB, ST7FLITE-SK/RAIS, ST7MDT10-DVP3, ST7MDT10-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit
• For Use With: 497-5858 - EVAL BOARD PLAYBACK ST7FLITE497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-4852

ST7LITE0xY0, ST7LITESxY0
11 ON-CHIP PERIPHERALS
11.1 LITE TIMER (LT)
11.1.1 Introduction
The Lite Timer can be used for general-purpose
timing functions. It is based on a free-running 8-bit
upcounter with two software-selectable timebase
periods, an 8-bit input capture register and watch-
dog function.
11.1.2 Main Features
■
■
Figure 31. Lite Timer Block Diagram
48/124
1
LTIC
Realtime Clock
– 8-bit upcounter
– 1 ms or 2 ms timebase period (@ 8 MHz f
– Maskable timebase interrupt
Input Capture
– 8-bit input capture register (LTICR)
– Maskable interrupt with wakeup from Halt
Mode capability
f
OSC
/32
LTICR
8-bit UPCOUNTER
INPUT CAPTURE
REGISTER
8-bit
8
7
LTCSR
ICIE
f
f
LTIMER
LTIMER
/2
ICF
OSC
TB
)
1
0
f
To 12-bit AT TImer
WDG
Timebase
1 or 2 ms
(@ 8 MHz
f
OSC
TBIE
■
)
– Enabled by hardware or software (configura-
– Optional reset on HALT instruction (configura-
– Automatically resets the device unless disable
– Software reset (Forced Watchdog reset)
– Watchdog reset status flag
Watchdog
ble by option byte)
ble by option byte)
bit is refreshed
TBF
WDG
RF
WATCHDOG
LTIC INTERRUPT REQUEST
LTTB INTERRUPT REQUEST
WDGE
WDGD
0
WATCHDOG RESET