P89V51RB2FA,529 NXP Semiconductors, P89V51RB2FA,529 Datasheet - Page 20
![IC 80C51 MCU FLASH 16K 44-PLCC](/photos/6/98/69845/568-44-plcc_sot187-2_sml.jpg)
P89V51RB2FA,529
Manufacturer Part Number
P89V51RB2FA,529
Description
IC 80C51 MCU FLASH 16K 44-PLCC
Manufacturer
NXP Semiconductors
Series
89Vr
Datasheet
1.P89V51RC2FBC557.pdf
(80 pages)
Specifications of P89V51RB2FA,529
Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-PLCC
Processor Series
P89V5x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Operating Supply Voltage
5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
For Use With
622-1017 - BOARD 44-ZIF PLCC SOCKET622-1001 - USB IN-CIRCUIT PROG 80C51ISP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
568-2427-5
935278706529
P89V51RB2FA-S
935278706529
P89V51RB2FA-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
P89V51RB2FA,529
Manufacturer:
NXP Semiconductors
Quantity:
10 000
NXP Semiconductors
P89V51RB2_RC2_RD2_5
Product data sheet
6.3.1 Flash organization
6.3.2 Boot block (block 1)
6.3 Flash memory IAP
Table 10.
Not bit addressable; Reset value 00H
Table 11.
The P89V51RB2/RC2/RD2 program memory consists of a 16/32/64 kB block. ISP
capability, in a second 8 kB block, is provided to allow the user code to be programmed
in-circuit through the serial port. There are three methods of erasing or programming of
the flash memory that may be used. First, the flash may be programmed or erased in the
end-user application by calling low-level routines through a common entry point (IAP).
Second, the on-chip ISP bootloader may be invoked. This ISP bootloader will, in turn, call
low-level routines through the same common entry point that can be used by the end-user
application. Third, the flash may be programmed or erased using the parallel method by
using a commercially available EPROM programmer which supports this device.
When the microcontroller programs its own flash memory, all of the low level details are
handled by code that is contained in block 1. A user program calls the common entry point
in the block 1 with appropriate parameters to accomplish the desired operation. Boot block
operations include erase user code, program user code, program security bits, etc.
Bit
7 to 4
3
2
1
0
Bit
Symbol
Fig 7. Dual data pointer organization
AUXR1 - Auxiliary register 1 (address A2H) bit allocation
-
AUXR1 - Auxiliary register 1 (address A2H) bit description
Symbol
-
GF2
0
-
DPS
7
DPS = 0
DPS = 1
AUXR1 / bit0
-
Rev. 05 — 12 November 2009
DPS
6
DPTR0
DPTR1
Description
Reserved for future use. Should be set to ‘0’ by user programs.
General purpose user-defined flag.
This bit contains a hard-wired ‘0’. Allows toggling of the DPS bit by
incrementing AUXR1, without interfering with other bits in the register.
Reserved for future use. Should be set to ‘0’ by user programs.
Data pointer select. Chooses one of two Data Pointers for use by the
program. See text for details.
-
5
DPH
83H
-
P89V51RB2/RC2/RD2
4
DPL
82H
8-bit microcontrollers with 80C51 core
DPTR1
DPTR0
GF2
3
external data memory
0
2
002aaa518
-
© NXP B.V. 2009. All rights reserved.
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