DSPIC30F5016-30I/PT Microchip Technology, DSPIC30F5016-30I/PT Datasheet - Page 92

• Manufacturer Part Number: DSPIC30F5016-30I/PT
• Description: IC DSPIC MCU/DSP 66K 80TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5016-30I/PT

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 68
• Program Memory Size: 66KB (22K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: I2C, SPI, UART
• No. Of I/o's: 68
• Flash Memory Size: 66KB
• Supply Voltage Range: 2.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164320 - MODULE SKT MPLAB PM3 80TQFPAC30F007 - MODULE SKT FOR DSPIC30F 80TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: DSPIC30F501630IPT

dsPIC30F5015/5016
14.7.2
When the CPU is placed in the Idle mode and the QEI
module is configured in the 16-bit Timer mode, the
16-bit
(QEICON<13>) = 0. This bit defaults to a logic ‘0’ upon
executing POR and BOR. For halting the timer module
during the CPU Idle mode, QEISIDL should be set
to ‘1’.
If the QEISIDL bit is cleared, the timer will function
normally, as if the CPU Idle mode had not been
entered.
DS70149D-page 92
timer
TIMER OPERATION DURING CPU
IDLE MODE
will
operate
if
the
QEISIDL
bit
14.8
The Quadrature Encoder Interface has the ability to
generate an interrupt on occurrence of the following
events:
• Interrupt on 16-bit up/down position counter
• Detection of qualified index pulse, or if CNTERR
• Timer period match event (overflow/underflow)
• Gate accumulation event
The QEI Interrupt Flag bit, QEIIF, is asserted upon
occurrence of any of the above events. The QEIIF bit
must be cleared in software. QEIIF is located in the
IFS2 Status register.
Enabling an interrupt is accomplished via the
respective enable bit, QEIIE. The QEIIE bit is located in
the IEC2 Control register.
rollover/underflow
bit is set
Quadrature Encoder Interface
Interrupts
© 2008 Microchip Technology Inc.