PIC18LF4431-I/P Microchip Technology, PIC18LF4431-I/P Datasheet - Page 50
![IC PIC MCU FLASH 8KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4431-I/P
Manufacturer Part Number
PIC18LF4431-I/P
Description
IC PIC MCU FLASH 8KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(4 pages)
8.PIC18LF2331-ISO.pdf
(40 pages)
9.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18LF4431-I/P
Core Size
8-Bit
Program Memory Size
16KB (8K x 16)
Oscillator Type
Internal
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 9x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
1 x 8
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4431-I/P
Manufacturer:
Microchip Technology
Quantity:
135
Company:
Part Number:
PIC18LF4431-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18LF2331-ISO PDF datasheet #8
- PIC18F4331-EP PDF datasheet #9
- Current page: 50 of 400
- Download datasheet (7Mb)
PIC18F2331/2431/4331/4431
4.1
A Power-on Reset pulse is generated on-chip when
V
circuitry, just tie the MCLR pin through a resistor (1k to
10 kΩ) to V
nents usually needed to create a Power-on Reset
delay. A minimum rise rate for V
(parameter D004). For a slow rise time, see Figure 4-2.
When the device starts normal operation (i.e., exits the
Reset condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in Reset until the operating
conditions are met.
FIGURE 4-2:
DS39616C-page 48
DD
Note:
Note 1: External Power-on Reset circuit is
rise is detected. To take advantage of the POR
V
2: R < 40 kΩ is recommended to make
3: R1 ≥ 1 kΩ will limit any current flowing
DD
Power-on Reset (POR)
D
DD
The following decoupling method is
recommended:
1. A 1 μF capacitor should be connected
2. A
required only if the V
is too slow. The diode D helps discharge
the capacitor quickly when V
down.
sure that the voltage drop across R does
not violate the device’s electrical specifi-
cation.
into MCLR from external capacitor C, in
the event of MCLR/V
due to Electrostatic Discharge (ESD) or
Electrical Overstress (EOS).
. This will eliminate external RC compo-
across AV
connected across V
V
DD
R
C
similar
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
DD
R1
and AV
capacitor
DD
PIC18FXXXX
DD
MCLR
PP
DD
SS
POWER-UP)
power-up slope
pin breakdown,
DD
.
and V
should
DD
is specified
SS
powers
.
Preliminary
be
4.2
The Power-up Timer (PWRT) of the PIC18F2331/2431/
4331/4431 devices is an 11-bit counter, which uses the
INTRC source as the clock input. This yields a count of
2048 x 32 μs = 65.6 ms. While the PWRT is counting,
the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 for details.
The PWRT is enabled by clearing Configuration bit
PWRTEN.
4.3
The Oscillator Start-up Timer (OST) provides a
1024 oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33). This ensures that
the crystal oscillator or resonator has started and
stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes, and only on Power-on Reset or on exit
from most power-managed modes.
4.4
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly
different from other oscillator modes. A portion of the
Power-up Timer is used to provide a fixed time-out that
is sufficient for the PLL to lock to the main oscillator
frequency. This PLL lock time-out (T
2 ms and follows the oscillator start-up time-out.
4.5
A Configuration bit, BOREN, can disable (if clear/
programmed) or enable (if set) the Brown-out Reset
circuitry. If V
through D005K) for greater than T
the brown-out situation will reset the chip. A Reset may
not occur if V
The chip will remain in Brown-out Reset until V
above V
invoked after V
the chip in Reset for an additional time delay T
(parameter 33). If V
Power-up Timer is running, the chip will go back into a
Brown-out Reset and the Power-up Timer will be
initialized. Once V
Timer will execute the additional time delay. Enabling
the Brown-out Reset does not automatically enable the
PWRT.
BOR
Power-up Timer (PWRT)
Oscillator Start-up Timer (OST)
PLL Lock Time-out
Brown-out Reset (BOR)
. If the Power-up Timer is enabled, it will be
DD
DD
DD
falls below V
falls below V
DD
rises above V
DD
rises above V
© 2007 Microchip Technology Inc.
drops below V
BOR
BOR
BOR
BOR
for less than T
(parameter D005A
BOR
; it then will keep
PLL
(parameter 35),
, the Power-up
BOR
) is typically
while the
DD
PWRT
rises
BOR
.
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