PIC18F4331-I/P Microchip Technology, PIC18F4331-I/P Datasheet - Page 243
![IC PIC MCU FLASH 4KX16 40DIP](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18F4331-I/P
Manufacturer Part Number
PIC18F4331-I/P
Description
IC PIC MCU FLASH 4KX16 40DIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC16F818-ISO.pdf
(6 pages)
3.PIC18F2331-ISO.pdf
(392 pages)
4.PIC18F2331-ISO.pdf
(8 pages)
5.PIC18F2331-ISO.pdf
(6 pages)
6.PIC18F2331-ISO.pdf
(16 pages)
7.PIC18LF2331-ISO.pdf
(40 pages)
8.PIC18F4331-EP.pdf
(400 pages)
Specifications of PIC18F4331-I/P
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
Number Of I /o
36
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 9x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Controller Family/series
PIC18
No. Of I/o's
36
Eeprom Memory Size
256Byte
Ram Memory Size
768Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
EUSART, I2C, SPI, SSP
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
9 bit
Package
40PDIP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
I3-DB18F4431 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F4331-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F4331-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC16F818-ISO PDF datasheet #2
- PIC18F2331-ISO PDF datasheet #3
- PIC18F2331-ISO PDF datasheet #4
- PIC18F2331-ISO PDF datasheet #5
- PIC18F2331-ISO PDF datasheet #6
- PIC18LF2331-ISO PDF datasheet #7
- PIC18F4331-EP PDF datasheet #8
- Current page: 243 of 400
- Download datasheet (7Mb)
19.4.2
Once Synchronous mode is selected, reception is
enabled by setting either the Single Receive Enable bit,
SREN (RCSTA<5>) or the Continuous Receive Enable
bit, CREN (RCSTA<4>). Data is sampled on the RC7/
RX/DT/SDO pin on the falling edge of the clock.
If enable bit SREN is set, only a single word is received.
If enable bit CREN is set, the reception is continuous
until CREN is cleared. If both bits are set, then CREN
takes precedence.
To set up a Synchronous Master Reception:
1.
2.
FIGURE 19-12:
TABLE 19-8:
© 2007 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
RCSTA
RCREG
TXSTA
BAUDCTL
SPBRGH
SPBRG
Legend:
Note:
RC7/RX/DT/SDO
Name
RC6/TX/CK/SS
RC6/TX/CK/SS
Initialize the SPBRGH:SPBRG registers for the
appropriate baud rate. Set or clear the BRGH
and BRG16 bits, as required, to achieve the
desired baud rate.
Enable the synchronous master serial port by
setting bits, SYNC, SPEN and CSRC.
(SCKP = 0)
(SCKP = 1)
(Interrupt)
CREN bit
bit SREN
SREN bit
RCIF bit
RXREG
Write to
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
x = unknown, - = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
EUSART Receive Register
EUSART Baud Rate Generator Register High Byte
EUSART Baud Rate Generator Register Low Byte
Read
EUSART SYNCHRONOUS MASTER
RECEPTION
GIE/GIEH PEIE/GIEL
Pin
Pin
Pin
CSRC
SPEN
Bit 7
—
—
—
—
Q2
REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
‘0’
SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
bit 0
TMR0IE
SREN
TXEN
RCIE
RCIP
RCIF
Bit 5
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
bit 1
INT0IE
CREN
SYNC
SCKP
PIC18F2331/2431/4331/4431
Bit 4
TXIF
TXIE
TXIP
Preliminary
bit 2
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
bit 3
TMR0IF
CCP1IE
CCP1IP
CCP1IF
3.
4.
5.
6.
7.
8.
9.
10. If any error occurred, clear the error by clearing
11. If using interrupts, ensure that the GIE and PEIE
BRGH
FERR
Bit 2
—
Ensure bits, CREN and SREN, are clear.
If interrupts are desired, set enable bit, RCIE.
If 9-bit reception is desired, set bit, RX9.
If a single reception is required, set bit, SREN.
For continuous reception, set bit, CREN.
Interrupt flag bit, RCIF, will be set when
reception is complete and an interrupt will be
generated if the enable bit, RCIE, was set.
Read the RCSTA register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
bit, CREN.
bits in the INTCON register (INTCON<7:6>) are
set.
bit 4
TMR2IE
TMR2IP
TMR2IF
INT0IF
OERR
TRMT
WUE
Bit 1
bit 5
TMR1IF
TMR1IE
TMR1IP
ABDEN
RX9D
TX9D
RBIF
Bit 0
bit 6
0000 000x
-000 0000
-000 0000
-111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
POR, BOR
Value on
DS39616C-page 241
bit 7
0000 000u
-000 0000
-000 0000
-111 1111
0000 000x
0000 0000
0000 0010
-1-1 0-00
0000 0000
0000 0000
Q1 Q2 Q3 Q4
Value on
all other
Resets
‘0’
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