PIC18F4331-I/P Microchip Technology, PIC18F4331-I/P Datasheet - Page 179

• Manufacturer Part Number: PIC18F4331-I/P
• Description: IC PIC MCU FLASH 4KX16 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4331-I/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, Power Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 768 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 9x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC18
• No. Of I/o's: 36
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 768Byte
• Cpu Speed: 40MHz
• No. Of Timers: 4
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 768 B
• Interface Type: EUSART, I2C, SPI, SSP
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 9 bit
• Package: 40PDIP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB18F4431 - BOARD DAUGHTER ICEPIC3DVA18XP400 - DEVICE ADAPTER 18F4220 PDIP 40LD444-1001 - DEMO BOARD FOR PICMICRO MCUACICE0206 - ADAPTER MPLABICE 40P 600 MIL
• Lead Free Status / Rohs Status: Details

16.3
The Motion Feedback Module includes three noise
rejection filters on CAP1/INDX, CAP2/QEA and
CAP3/QEB. The filter block also includes a fourth filter
for the T5CKI pin. They are intended to help reduce
spurious noise spikes which may cause the input sig-
nals to become corrupted at the inputs. The filter
ensures that the input signals are not permitted to
change until a stable value has been registered for
three consecutive sampling clock cycles.
The filters are controlled using the Digital Filter Control
(DFLTCON) register (see Register 16-3). The filters
can be individually enabled or disabled by setting or
clearing the corresponding FLTxEN bit in the
DFLTCON register. The sampling frequency, which
must be the same for all three noise filters, can be
REGISTER 16-3:
© 2007 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
Note 1:
Note:
U-0
—
Noise Filters
Noise filter output enables are functional in both QEI and IC Operating modes.
The Noise Filter is intended for random high-frequency filtering and not continuous high-frequency filtering.
Unimplemented: Read as ‘0’
FLT4EN: Noise Filter Output Enable bit, T5CKI Input
1 = Enabled
0 = Disabled
FLT3EN: Noise Filter Output Enable bit, CAP3/QEB Input
1 = Enabled
0 = Disabled
FLT2EN: Noise Filter Output Enable bit, CAP2/QEA Input
1 = Enabled
0 = Disabled
FLT1EN: Noise Filter Output Enable bit, CAP1/INDX Input
1 = Enabled
0 = Disabled
FLTCK<2:0>: Noise Filter Clock Divider Ratio bits
111 = Unused
110 = 1:128
101 = 1:64
100 = 1:32
011 = 1:16
010 = 1:4
001 = 1:2
000 = 1:1
FLT4EN
R/W-0
DFLTCON: DIGITAL FILTER CONTROL REGISTER
W = Writable bit
‘1’ = Bit is set
FLT3EN
R/W-0
(1)
PIC18F2331/2431/4331/4431
FLT2EN
R/W-0
Preliminary
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
FLT1EN
R/W-0
programmed by the FLTCK2:FLTCK0 Configuration
bits. T
divider block.
The noise filters can either be added or removed from
the input capture or QEI signal path by setting or
clearing the appropriate FLTxEN bit, respectively. Each
capture channel provides for individual enable control
of the filter output. The FLT4EN bit enables or disabled
the noise filter available on T5CKI input in the Timer5
module.
The filter network for all channels is disabled on
Power-on and Brown-out Resets, as the DFLTCON
register is cleared on Resets. The operation of the filter
is shown in the timing diagram in Figure 16-14.
(1)
CY
(1)
(1)
(1)
is used as the clock reference to the clock
FLTCK2
R/W-0
x = Bit is unknown
FLTCK1
R/W-0
DS39616C-page 177
FLTCK0
R/W-0
bit 0