DSPIC33FJ32MC204-I/ML Microchip Technology, DSPIC33FJ32MC204-I/ML Datasheet - Page 215

• Manufacturer Part Number: DSPIC33FJ32MC204-I/ML
• Description: IC DSPIC MCU/DSP 32K 44QFN
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32MC204-I/ML

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 44-QFN
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 35
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 9x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 35
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DM240002, DM330011, DM330021, MA330017
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

21.2
The
dsPIC33FJ16MC304 devices power their core digital
logic at a nominal 2.5V. This can create a conflict for
designs that are required to operate at a higher typical
voltage, such as 3.3V. To simplify system design, all
devices
dsPIC33FJ16MC304 family incorporate an on-chip
regulator that allows the device to run its core logic from
V
The regulator provides power to the core from the other
V
(less than 5 ohms) capacitor (such as tantalum or
ceramic) must be connected to the V
(Figure 21-1). This helps to maintain the stability of the
regulator. The recommended value for the filter capac-
itor is provided in Table 24-13 located in Section 24.1
“DC Characteristics”.
On a POR
voltage regulator to generate an output voltage. During
this time, designated as T
disabled. T
resumes operation after any power-down.
FIGURE 21-1:
 2009 Microchip Technology Inc.
DD
DD
Note:
Note 1:
.
pins. When the regulator is enabled, a low-ESR
2:
On-Chip Voltage Regulator
C
,
EFC
in
STARTUP
it takes approximately 20 s for the on-chip
It is important for low-ESR capacitors to be
placed as close as possible to the
V
dsPIC33FJ32MC202/204 and dsPIC33FJ16MC304
CAP
These are typical operating voltages. Refer
to Table 24-13 located in Section 24.1 “DC
Characteristics” for the full operating
ranges of V
It is important for low-ESR capacitors to be
placed as close as possible to the
V
dsPIC33FJ32MC202/204
3.3V
CAP
the
/V
/V
DDCORE
DDCORE
is applied every time the device
dsPIC33FJ32MC202/204
CONNECTIONS FOR THE
ON-CHIP VOLTAGE
REGULATOR
V
V
V
DD
DD
CAP
SS
dsPIC33F
and V
STARTUP
pin.
pin.
/V
DDCORE
CAP
, code execution is
/V
DDCORE
CAP
(1)
/V
DDCORE
.
and
and
Preliminary
pin
21.3
The Brown-out Reset (BOR) module is based on an
internal voltage reference circuit that monitors the reg-
ulated supply voltage V
pose of the BOR module is to generate a device Reset
when a brown-out condition occurs. Brown-out condi-
tions are generally caused by glitches on the AC mains
(for example, missing portions of the AC cycle wave-
form due to bad power transmission lines, or voltage
sags due to excessive current draw when a large
inductive load is turned on).
A BOR generates a Reset pulse, which resets the
device. The BOR selects the clock source, based on
the device Configuration bit values (FNOSC<2:0> and
POSCMD<1:0>).
If an oscillator mode is selected, the BOR activates the
Oscillator Start-up Timer (OST). The system clock is
held until OST expires. If the PLL is used, the clock is
held until the LOCK bit (OSCCON<5>) is ‘1’.
Concurrently, the PWRT time-out (TPWRT) is applied
before the internal Reset is released. If TPWRT = 0 and
a crystal oscillator is being used, then a nominal delay
of TFSCM = 100 is applied. The total delay in this case
is TFSCM.
The BOR Status bit (RCON<1>) is set to indicate that a
BOR has occurred. The BOR circuit continues to oper-
ate while in Sleep or Idle modes and resets the device
should VDD fall below the BOR threshold voltage.
BOR: Brown-Out Reset
CAP
/V
DDCORE
DS70283G-page 215
. The main pur-