DSPIC30F2012-20I/SP Microchip Technology, DSPIC30F2012-20I/SP Datasheet - Page 23
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DSPIC30F2012-20I/SP
Manufacturer Part Number
DSPIC30F2012-20I/SP
Description
IC DSPIC MCU/DSP 12K 28DIP
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F2011-20ISO.pdf
(66 pages)
2.DSPIC30F2011-20ISO.pdf
(210 pages)
3.DSPIC30F2011-20ISO.pdf
(14 pages)
4.DSPIC30F2011-20ISO.pdf
(6 pages)
5.DSPIC30F2011-20ISO.pdf
(18 pages)
6.DSPIC30F2011-20ISO.pdf
(206 pages)
Specifications of DSPIC30F2012-20I/SP
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
20
Program Memory Size
12KB (4K x 24)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-DIP (0.300", 7.62mm)
Core Frequency
40MHz
Embedded Interface Type
I2C, SPI, UART
No. Of I/o's
20
Flash Memory Size
12KB
Supply Voltage Range
2.5V To 5.5V
Operating Temperature Range
-40°C To
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
DSPIC30F201220ISP
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F2012-20I/SP
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
DSPIC30F2012-20I/SP
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- DSPIC30F2011-20ISO PDF datasheet
- DSPIC30F2011-20ISO PDF datasheet #2
- DSPIC30F2011-20ISO PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20ISO PDF datasheet #5
- DSPIC30F2011-20ISO PDF datasheet #6
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- Download datasheet (4Mb)
2.4
The DSP engine consists of a high speed 17-bit x
17-bit multiplier, a barrel shifter and a 40-bit adder/
subtracter (with two target accumulators, round and
saturation logic).
The DSP engine also has the capability to perform
inherent
which require no additional data. These instructions are
ADD, SUB and NEG.
The dsPIC30F is a single-cycle instruction flow archi-
tecture, threfore, concurrent operation of the DSP
engine with MCU instruction flow is not possible.
However, some MCU ALU and DSP engine resources
may be used concurrently by the same instruction (e.g.,
ED, EDAC).
TABLE 2-2:
© 2005 Microchip Technology Inc.
DSP Engine
Instruction
accumulator-to-accumulator
MOVSAC
MPY.N
EDAC
MAC
MAC
MPY
MSC
CLR
ED
DSP INSTRUCTION SUMMARY
dsPIC30F2011/2012/3012/3013
operations,
Algebraic Operation
Preliminary
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
A = A + x
No change in A
A = x * y
A = – x * y
A = A – x * y
2
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
1.
2.
3.
4.
5.
6.
7.
A block diagram of the DSP engine is shown in
Figure 2-2.
2
Note:
2
Fractional or integer DSP multiply (IF).
Signed or unsigned DSP multiply (US).
Conventional or convergent rounding (RND).
Automatic saturation on/off for AccA (SATA).
Automatic saturation on/off for AccB (SATB).
Automatic saturation on/off for writes to data
memory (SATDW).
Accumulator
(ACCSAT).
For CORCON layout, see Table 3-3.
Saturation
mode
ACC WB?
DS70139C-page 21
Yes
Yes
Yes
Yes
No
No
No
No
No
selection
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