PIC24FJ32GA002-E/ML Microchip Technology, PIC24FJ32GA002-E/ML Datasheet - Page 100
![IC PIC MCU FLASH 32K 28-QFN](/photos/6/81/68120/150-28-qfn_sml.jpg)
PIC24FJ32GA002-E/ML
Manufacturer Part Number
PIC24FJ32GA002-E/ML
Description
IC PIC MCU FLASH 32K 28-QFN
Manufacturer
Microchip Technology
Series
PIC® 24Fr
Datasheets
1.PIC24FJ16GA002-ISS.pdf
(52 pages)
2.PIC24FJ16GA002-ISS.pdf
(268 pages)
3.PIC24FJ16GA002-ISS.pdf
(22 pages)
4.PIC24FJ64GA004-EPT.pdf
(262 pages)
Specifications of PIC24FJ32GA002-E/ML
Program Memory Type
FLASH
Program Memory Size
32KB (11K x 24)
Package / Case
28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
Core Processor
PIC
Core Size
16-Bit
Speed
32MHz
Connectivity
I²C, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
21
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
PIC24FJ
Core
PIC
Data Bus Width
16 bit
Data Ram Size
8 KB
Interface Type
I2C, IrDA, SPI, UART
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
21
Number Of Timers
5
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240011, DM300027, DV164033, MA240013, AC164127, DM240002
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 10 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM240011 - KIT STARTER MPLAB FOR PIC24F MCUAC162088 - HEADER MPLAB ICD2 24FJ64GA004 28AC164336 - MODULE SOCKET FOR PM3 28/44QFNDV164033 - KIT START EXPLORER 16 MPLAB ICD2
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC24FJ32GA002-E/ML
Manufacturer:
Microchip Technology
Quantity:
135
Part Number:
PIC24FJ32GA002-E/ML
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC24FJ16GA002-ISS PDF datasheet
- PIC24FJ16GA002-ISS PDF datasheet #2
- PIC24FJ16GA002-ISS PDF datasheet #3
- PIC24FJ64GA004-EPT PDF datasheet #4
- Current page: 100 of 268
- Download datasheet (2Mb)
PIC24FJ64GA004 FAMILY
REGISTER 8-3:
8.4
With few limitations, applications are free to switch
between any of the four clock sources (POSC, SOSC,
FRC and LPRC) under software control and at any
time. To limit the possible side effects that could result
from this flexibility, PIC24F devices have a safeguard
lock built into the switching process.
DS39881D-page 100
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-6
bit 5-0
Note 1:
Note:
U-0
U-0
—
—
Clock Switching Operation
Increments or decrements of TUN5:TUN0 may not change the FRC frequency in equal steps over the
FRC tuning range, and may not be monotonic.
The primary oscillator mode has three
different submodes (XT, HS and EC)
which are determined by the POSCMDx
Configuration bits. While an application
can switch to and from primary oscillator
mode in software, it cannot switch
between the different primary submodes
without reprogramming the device.
Unimplemented: Read as ‘0’
TUN5:TUN0: FRC Oscillator Tuning bits
011111 = Maximum frequency deviation
011110 =
000001 =
000000 = Center frequency, oscillator is running at factory calibrated frequency
111111 =
100001 =
100000 = Minimum frequency deviation
U-0
U-0
—
—
OSCTUN: FRC Oscillator Tune Register
W = Writable bit
‘1’ = Bit is set
TUN5
R/W-0
U-0
—
(1)
TUN4
R/W-0
U-0
—
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
TUN3
R/W-0
8.4.1
To enable clock switching, the FCKSM1 Configuration
bit in Flash Configuration Word 2 must be programmed
to ‘0’. (Refer to Section 24.1 “Configuration Bits” for
further details.) If the FCKSM1 Configuration bit is
unprogrammed (‘1’), the clock switching function and
Fail-Safe Clock Monitor function are disabled. This is
the default setting.
The NOSCx control bits (OSCCON<10:8>) do not
control the clock selection when clock switching is dis-
abled. However, the COSCx bits (OSCCON<14:12>)
will reflect the clock source selected by the FNOSCx
Configuration bits.
The OSWEN control bit (OSCCON<0>) has no effect
when clock switching is disabled. It is held at ‘0’ at all
times.
U-0
—
(1)
ENABLING CLOCK SWITCHING
TUN2
R/W-0
U-0
—
(1)
2010 Microchip Technology Inc.
x = Bit is unknown
TUN1
R/W-0
U-0
—
(1)
TUN0
R/W-0
U-0
—
(1)
bit 8
bit 0
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