DSPIC30F2011-30I/P Microchip Technology, DSPIC30F2011-30I/P Datasheet
DSPIC30F2011-30I/P
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... Microchip Technology Inc. Data Sheet High-Performance, 16-Bit Digital Signal Controllers DS70139E ...
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... Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... High-Performance Digital Signal Controllers Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “ ...
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... Sensor Family Program Memory Device Pins Bytes Instructions dsPIC30F2011 18 12K 4K dsPIC30F3012 18 24K 8K dsPIC30F2012 28 12K 4K dsPIC30F3013 28 24K 8K Pin Diagrams 18-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin PDIP and SOIC EMUD3/AN0/V EMUC3/AN1/V AN2/SS1/LVDIN/CN4/RB2 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 28-Pin SPDIP and SOIC ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F2011 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 7 15 DS70139E-page 3 ...
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... Pin Diagrams 28-Pin QFN AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 AN4/CN6/RB4 AN5/CN7/RB5 OSC1/CLKI OSC2/CLKO/RC15 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139E-page AN8/OC1/RB8 2 20 AN9/OC2/RB9 3 CN17/RF4 19 dsPIC30F2012 4 CN18/RF5 PGC/EMUC/U1RX/SDI1/SDA/RF2 7 15 © 2006 Microchip Technology Inc. ...
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... Pin Diagram 44-Pin QFN PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 dsPIC30F3012 OSC2/CLKO/RC15 32 OSC1/CLKI AN3/CN5/RB3 AN2/SS1/LVDIN/CN4/RB2 DS70139E-page 5 ...
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... Pin Diagrams 44-Pin QFN PGC/EMUC/U1RX/SDI1/SDA/RF2 U2TX/CN18/RF5 U2RX/CN17/RF4 AN9/OC2/RB9 AN8/OC1/RB8 Note: For descriptions of individual pins, see Section 1.0 “Device Overview”. DS70139E-page dsPIC30F3013 OSC2/CLKO/RC15 OSC1/CLKI AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 NC AN2/SS1/LVDIN/CN4/RB2 © 2006 Microchip Technology Inc. ...
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... When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 7 ...
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... NOTES: DS70139E-page 8 © 2006 Microchip Technology Inc. ...
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... The following block diagrams depict the architecture for these devices: • Figure 1-1 illustrates the dsPIC30F2011 • Figure 1-2 illustrates the dsPIC30F2012 • Figure 1-3 illustrates the dsPIC30F3012 • Figure 1-4 illustrates the dsPIC30F3013 Following the block diagrams, Table 1-1 relates the I/O functions to pinout information ...
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... PIC30F2011/2012/3012/3013 ds FIGURE 1-1: dsPIC30F2011 BLOCK DIAGRAM Y Data Bus Interrupt PSV & Table Controller Data Access 8 24 Control Block 24 24 PCU PCH Program Counter Stack Address Latch Control Logic Program Memory (12 Kbytes) Data Latch 16 ROM Latch 24 16 Instruction Decode & Control Power-up ...
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... Oscillator OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (512 bytes) (512 bytes) 16 Address Address Latch Latch RAGU ...
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... W Reg Array Decode PORTC 16 16 DSP Divide Engine Unit ALU<16> PORTD Input Output 2 Compare I C™ Module Timers SPI1 UART1 EMUD3/AN0/V +/CN2/RB0 REF EMUC3/AN1/V -/CN3/RB1 REF AN2/SS1/LVDIN/CN4/RB2 AN3/CN5/RB3 PGD/EMUD/AN4/U1TX/SDO1/SCL/CN6/RB4 PGC/EMUC/AN5/U1RX/SDI1/SDA/CN7/RB5 AN6/SCK1/INT0/OCFA/RB6 EMUD2/AN7/OC2/IC2/INT2/RB7 EMUD1/SOSCI/T2CK/U1ATX/CN1/RC13 EMUC1/SOSCO/T1CK/U1ARX/CN0/RC14 OSC2/CLKO/RC15 EMUC2/OC1/IC1/INT1/RD0 © 2006 Microchip Technology Inc. ...
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... Oscillator Timing OSC1/CLKI Generation Start-up Timer POR/BOR Reset Watchdog MCLR Timer Low-Voltage Detect 12-bit ADC Capture Module © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 X Data Bus Data Latch Data Latch X Data Y Data 16 RAM RAM (1 Kbytes) (1 Kbytes) 16 Address Address Latch Latch RAGU Y AGU ...
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... PORTC is a bidirectional I/O port. ST PORTD is a bidirectional I/O port. ST PORTF is a bidirectional I/O port. ST Synchronous serial clock input/output for SPI1. ST SPI1 Data In. — SPI1 Data Out. ST SPI1 Slave Synchronization. Analog = Analog input O = Output P = Power Description © 2006 Microchip Technology Inc. ...
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... REF Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels I = Input © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Buffer Type ST Synchronous serial clock input/output for I ST Synchronous serial data input/output for I — 32 kHz low-power oscillator crystal output. ST/CMOS 32 kHz low-power oscillator crystal input. ST buffer when configured in RC mode ...
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... PIC30F2011/2012/3012/3013 ds NOTES: DS70139E-page 16 © 2006 Microchip Technology Inc. ...
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... Each data word consists of 2 bytes and most instructions can address data either as words or bytes. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Two ways to access data in program memory are: • The upper 32 Kbytes of data space memory can be mapped into the lower half (user space) of ...
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... The upper byte of the STATUS register contains the DSP Adder/Subtracter Status bits, the DO Loop Active bit (DA) and the Digit Carry (DC) Status bit. 2.2.3 PROGRAM COUNTER The program counter is 23 bits wide; bit 0 is always clear. Therefore, the PC can address instruction words. © 2006 Microchip Technology Inc. ...
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... DSP ACCA Accumulators ACCB PC22 0 7 TABPAG TBLPAG Data Table Page Address 7 0 PSVPAG PSVPAG OAB SAB DA SRH © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 D15 D0 W0/WREG W10 W11 W12/DSP Offset W13/DSP Write-Back W14/Frame Pointer W15/Stack Pointer SPLIM AD15 AD31 PC0 0 Program Space Visibility Page Address ...
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... DIV/ DIVF instruction. Thus, a complete divide operation requires 19 cycles. Note: The divide flow is interruptible. However, the user needs to save the context as appropriate. Function W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 W0; Rem W1 © 2006 Microchip Technology Inc. ...
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... EDAC MAC MAC MOVSAC MPY MPY.N MSC © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The DSP engine has various options selected through various bits in the CPU Core Configuration register (CORCON), as listed below: 1. Fractional or integer DSP multiply (IF). 2. Signed or unsigned DSP multiply (US). ...
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... PIC30F2011/2012/3012/3013 ds FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40 Carry/Borrow Out Carry/Borrow In DS70139E-page 22 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel 16 Shifter 40 Sign-Extend 17-bit Multiplier/Scaler 16 16 To/From W Array Round u Logic Zero Backfill © 2006 Microchip Technology Inc. ...
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... For the ADD and LAC instructions, the data to be accumulated or loaded can be optionally scaled via the barrel shifter prior to accumulation. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.2.1 The adder/subtracter is a 40-bit adder with an optional zero input into one side and either true or complement data into the other input ...
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... Space Write Saturation”). Note that for the MAC class of instructions, the accumulator write-back operation functions in the same manner, addressing combined MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. © 2006 Microchip Technology Inc. ...
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... If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2.4.3 BARREL SHIFTER The barrel shifter is capable of performing up to 16-bit arithmetic or logic right shifts 16-bit left shifts in a single cycle ...
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... PIC30F2011/2012/3012/3013 ds NOTES: DS70139E-page 26 © 2006 Microchip Technology Inc. ...
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... Figure 3-1. The program space memory map for the dsPI30F3012/3013 is shown in Figure 3-2. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program memory is addressable by a 24-bit value from either the 23-bit PC, table instruction Effective Address (EA), or data space EA, when program space is mapped into data space as defined by Table 3-1 ...
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... FIGURE 3-1: dsPIC30F2011/2012 PROGRAM SPACE MEMORY MAP Reset - GOTO Instruction Reset - Target Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (4K instructions) Reserved (Read ‘0’s) Reserved UNITID (32 instr.) Reserved Device Configuration Registers Reserved DEVID (2) DS70139E-page 28 FIGURE 3-2: ...
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... Space Visibility Using 1/0 Table Instruction User/ Configuration Space Select Note: Program space visibility cannot be used to access bits <23:16> word in program memory. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Program Space Address <23> <22:16> 0 TBLPAG<7:0> TBLPAG<7:0> PSVPAG<7:0> bits Program Counter Select 1 EA ...
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... DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS This architecture fetches 24-bit wide program memory. Consequently, instructions are always However, as the architecture is modified Harvard, data can also be present in program space. There are two methods by which program space can be accessed: via special table instructions, or through the remapping of a 16K word program space page into the upper half of data space (see Section 3.1.2 “ ...
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... The upper 8 bits should be programmed to force an illegal instruction to maintain machine robustness. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for details on instruction encoding. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 TBLRDH TBLRDH.B (Wn<0> TBLRDH.B (Wn<0> ...
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... FIGURE 3-6: DATA SPACE WINDOW INTO PROGRAM SPACE OPERATION Data Space 15 EA<15> Data Space 15 EA EA<15> Upper Half of Data Space is Mapped into Program Space BSET CORCON,#2 ; Set PSV bit MOV #0x0 Set PSVPAG register MOV W0, PSVPAG MOV 0x9200 Access program memory location ...
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... W8 and W9. Both address spaces are concurrently accessed only with the MAC class instructions. The data space memory map for the dsPIC30F2011 and dsPIC30F2012 is shown in Figure 3-7. The data space memory map for the dsPIC30F3012 and dsPIC30F3013 is shown in Figure 3-8. ...
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... FIGURE 3-8: dsPIC30F3012/3013 DATA SPACE MEMORY MAP MSB Address 0x0001 2 Kbyte SFR Space 0x07FF 0x0801 0x0BFF 2 Kbyte 0x0C01 SRAM Space 0x0FFF 0x1001 0x1FFF 0x8001 Optionally Mapped into Program Memory 0xFFFF DS70139E-page 34 LSB 16 bits Address MSB LSB 0x0000 SFR Space 0x07FE ...
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... DATA SPACE FOR MCU AND DSP (MAC CLASS) INSTRUCTIONS EXAMPLE SFR SPACE (Y SPACE) Non-MAC Class Ops (Read/Write) MAC Class Ops (Write) Indirect EA using any W © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 UNUSED Y SPACE UNUSED MAC Class Ops (Read) Indirect EA using W8, W9 SFR SPACE ...
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... DATA SPACES The X data space is used by all instructions and sup- ports all addressing modes. There are separate read and write data buses. The X read data bus is the return data path for all instructions that view data space as combined X and Y address space also the X address space data path for the dual operand read instructions (MAC class) ...
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... W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 There is a Stack Pointer Limit register (SPLIM) associ- ated with the Stack Pointer. SPLIM is uninitialized at Reset the case for the Stack Pointer, SPLIM<0> is forced to ‘0’ because all stack operations must be word aligned ...
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TABLE 3-3: CORE REGISTER MAP Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) W0 0000 W1 0002 W2 0004 W3 0006 W4 0008 W5 000A W6 000C W7 000E W8 0010 W9 0012 W10 0014 W11 ...
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TABLE 3-3: CORE REGISTER MAP (CONTINUED) Address SFR Name Bit 15 Bit 14 Bit 13 Bit 12 (Home) CORCON 0044 — — — US MODCON 0046 XMODEN YMODEN — XMODSRT 0048 XMODEND 004A YMODSRT 004C YMODEND 004E XBREV 0050 BREN ...
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... NOTES: DS70139E-page 40 © 2006 Microchip Technology Inc. ...
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... Register Indirect Pre-modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.1.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space) ...
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... MOVE AND ACCUMULATOR INSTRUCTIONS Move instructions and the DSP accumulator class of instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instruc- tions, move and accumulator instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode ...
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... Address 0x1100 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4.2.2 W ADDRESS REGISTER SELECTION The Modulo and Bit-Reversed Addressing Control reg- registers: ister, MODCON<15:0>, contains enable flags as well register field to specify the W address registers. ...
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... MODULO ADDRESSING APPLICABILITY Modulo Addressing can be applied to the Effective Address (EA) calculation associated with any W regis- ter important to realize that the address bound- aries check for addresses less than, or greater than the upper (for incrementing buffers), and lower (for decre- menting buffers) boundary addresses (not just equal to) ...
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... TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) 1024 512 256 128 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Sequential Address Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Bit-Reversed Address Decimal XB<14:0> Bit-Reversed Address Modifier Value ...
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... NOTES: DS70139E-page 46 © 2006 Microchip Technology Inc. ...
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... Addressing Using Table Instruction User/Configuration Space Select © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 5.2 Run-Time Self-Programming (RTSP) RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may erase program memory, 32 instructions (96 bytes time and can write program memory data, 32 instructions (96 bytes time ...
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... RTSP Operation The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instruc- tions or 96 bytes. Each panel consists of 128 rows instructions. RTSP allows the user to erase one row (32 instructions time and to program four instructions at one time. RTSP may be used to program multiple program memory panels, but the Table Pointer must be changed at each panel boundary ...
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... MOV W1 NVMKEY , BSET NVMCON,#WR NOP NOP © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 4. Write 32 instruction words of data from data RAM “image” into the program Flash write latches. 5. Program 32 instruction words into program Flash. a) Setup NVMCON register for multi-word, program Flash, program, and set WREN bit ...
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... LOADING WRITE LATCHES Example 5-2 shows a sequence of instructions that can be used to load the 96 bytes of write latches. 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the Table Pointer. EXAMPLE 5-2: LOADING WRITE LATCHES ; Set up a pointer to the first program memory location to be written ...
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TABLE 5-1: NVM REGISTER MAP File Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 NVMCON 0760 WR WREN WRERR NVMADR 0762 NVMADRU 0764 — — — NVMKEY 0766 — — — Legend: ...
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... NOTES: DS70139E-page 52 © 2006 Microchip Technology Inc. ...
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... Attempting to read the data EEPROM while a programming or erase operation is in progress results in unspecified data. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Control bit WR initiates write operations similar to pro- gram Flash writes. This bit cannot be cleared, only set, in software. They are cleared in hardware at the com- pletion of the write operation ...
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... Erasing Data EEPROM 6.2.1 ERASING A BLOCK OF DATA EEPROM In order to erase a block of data EEPROM, the NVMADRU and NVMADR registers must initially point to the block of memory to be erased. Configure NVMCON for erasing a block of data EEPROM and set the WR and WREN bits in the NVMCON register. ...
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... Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The write does not initiate if the above sequence is not exactly followed (write 0x55 to NVMKEY, write 0xAA to NVMCON, then set WR bit) for each word ...
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... EXAMPLE 6-5: DATA EEPROM BLOCK WRITE MOV #LOW_ADDR_WORD,W0 MOV #HIGH_ADDR_WORD,W1 MOV W1 TBLPAG , MOV #data1,W2 TBLWTL W2 [ W0]++ , MOV #data2,W2 TBLWTL W2 [ W0]++ , MOV #data3,W2 TBLWTL W2 [ W0]++ , MOV #data4,W2 TBLWTL W2 [ W0]++ , MOV #data5,W2 TBLWTL W2 [ W0]++ , MOV #data6,W2 TBLWTL W2 [ W0]++ , MOV #data7,W2 TBLWTL W2 [ W0]++ ...
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... WR Port Read LAT Read Port © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Any bit and its associated data and Control registers that are not valid for a particular device are disabled. That means the corresponding LATx and TRISx registers and the port pin read as zeros. ...
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... Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (output), the digital output level (V converted ...
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... TRISC 02CC TRISC15 TRISC14 TRISC13 — PORTC 02CE RC15 RC14 RC13 — LATC 02D0 LATC15 LATC14 LATC13 — TABLE 7-4: PORTD REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name TRISD 02D2 — — — — PORTD 02D4 — ...
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... PORTF 02E0 — — — — LATF 02E2 — — — — Note: The dsPIC30F2011/3012 do not have TRISF, PORTF or LATF. Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — — TRISD9 TRISD8 — — — — RD9 RD8 — ...
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... There are exter- nal signals (CN0 through CN7, CN17 and CN18) that may be selected (enabled) for generating an interrupt request on a change of state. TABLE 7-7: INPUT CHANGE NOTIFICATION REGISTER MAP FOR dsPIC30F2011/3012 (BITS 7-0) SFR Addr. Bit 7 Bit 6 ...
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... NOTES: DS70139E-page 62 © 2006 Microchip Technology Inc. ...
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... IPL bits. IPL<3> is present in the CORCON register, whereas IPL<2:0> are present in the STATUS register (SR) in the processor core. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 • INTCON1<15:0>, INTCON2<15:0> Global interrupt control functions are derived from these two registers. INTCON1 contains the con- trol and status flags for the processor exceptions ...
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... U2TX* — UART2 Transmitter 26-41 34-49 Reserved 42 50 LVD — Low-Voltage Detect 43-53 51-61 Reserved Lowest Natural Order Priority * Only the dsPIC30F3013 has UART2 and the U2RX, U2TX interrupts. These locations are reserved for the dsPIC30F2011/2012/3012. © 2006 Microchip Technology Inc. ...
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... Trap Lockout: Occurrence of multiple trap conditions simultaneously causes a Reset. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 8.3 Traps Traps can be considered as non-maskable interrupts indicating a software or hardware error, which adhere to a predefined priority as shown in Figure 8-1. They ...
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... Address Error Trap: This trap is initiated when any of the following circumstances occurs misaligned data word access is attempted data fetch from our unimplemented data memory location is attempted data access of an unimplemented program memory location is attempted instruction fetch from vector space is attempted. ...
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... The processor then loads the priority level for this inter- rupt into the STATUS register. This action disables all lower priority interrupts until the completion of the Interrupt Service Routine. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 FIGURE 8-2: 0x000000 0x000002 0x0000 15 ...
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... Fast Context Saving A context saving option is available using shadow reg- isters. Shadow registers are provided for the DC, N, OV, Z and C bits in SR, and the registers W0 through W3. The shadows are only one level deep. The shadow registers are accessible using the PUSH.S and POP.S instructions only ...
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... TABLE 8-2: dsPIC30F2011/2012/3012 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ADIF IFS1 0086 — — — ...
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TABLE 8-3: dsPIC30F3013 INTERRUPT CONTROLLER REGISTER MAP SFR ADR Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name INTCON1 0080 NSTDIS — — — — INTCON2 0082 ALTIVT DISI — — — IFS0 0084 CNIF MI2CIF SI2CIF NVMIF ...
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... SOSCO/ T1CK LPOSCEN SOSCI © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bit(s) in the 16-bit SFR, T1CON. Figure 9-1 presents a block diagram of the 16-bit timer module. 16-bit Timer Mode: In the 16-bit Timer mode, the timer ...
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... Timer Gate Operation The 16-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T1CK pin) is asserted high. Control bit, TGATE (T1CON<6>), must be set to enable this mode. The timer must be enabled (TON = 1) and the timer clock source set to internal (TCS = 0) ...
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... The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 9.5.2 RTC INTERRUPTS When an interrupt event occurs, the respective interrupt flag, T1IF, is asserted and an interrupt is generated if enabled ...
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TABLE 9-1: TIMER1 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 TMR1 0100 PR1 0102 T1CON 0104 TON — TSIDL — Legend uninitialized bit Note: Refer to “dsPIC30F Family Reference Manual” (DS70046) for ...
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... Timer3 interrupt enable bit (T3IE). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16-bit Timer Mode: In the 16-bit mode, Timer2 and Timer3 can be configured as two independent 16-bit timers. Each timer can be set up in either 16-bit Timer mode or 16-bit Synchronous Counter mode. See Section 9.0 “ ...
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... FIGURE 10-1: 32-BIT TIMER2/3 BLOCK DIAGRAM Data Bus<15:0> TMR3HLD Write TMR2 Read TMR2 16 Reset ADC Event Trigger Equal 0 T3IF Event Flag 1 TGATE (T2CON<6>) T2CK Note: Timer Configuration bit T32 (T2CON<3>) must be set to ‘ bits are respective to the T2CON register. DS70139E-page 76 ...
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... Equal Reset 0 T2IF Event Flag 1 TGATE T2CK FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM ADC Event Trigger Equal Reset 0 T3IF Event Flag 1 TGATE T3CK © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 PR2 Comparator x 16 TMR2 TGATE Gate Sync PR3 Comparator x 16 TMR3 TGATE ...
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... Timer Gate Operation The 32-bit timer can be placed in the Gated Time Accu- mulation mode. This mode allows the internal T increment the respective timer when the gate input sig- nal (T2CK pin) is asserted high. Control bit, TGATE (T2CON<6>), must be set to enable this mode. When in this mode, Timer2 is the originating clock source ...
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TABLE 10-1: TIMER2/3 REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON — TSIDL — T3CON 0112 TON — TSIDL — ...
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... NOTES: DS70139E-page 80 © 2006 Microchip Technology Inc. ...
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... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 These operating modes are determined by setting the appropriate bits in the IC1CON and IC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have two capture channels. 11.1 Simple Capture Event Mode The simple capture events in the dsPIC30F product family are: • ...
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... CAPTURE BUFFER OPERATION Each capture channel has an associated FIFO buffer which is four 16-bit words deep. There are two status flags which provide status on the FIFO buffer: • ICBNE — Input Capture Buffer Not Empty • ICOV — Input Capture Overflow ...
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TABLE 11-1: INPUT CAPTURE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 IC1BUF 0140 IC1CON 0142 — — ICSIDL — IC2BUF 0144 IC2CON 0146 — — ICSIDL — Legend uninitialized bit Note: Refer ...
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... NOTES: DS70139E-page 84 © 2006 Microchip Technology Inc. ...
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... Interrupt on Output Compare/PWM Event These operating modes are determined by setting the appropriate bits in the 16-bit OC1CON and OC2CON registers. The dsPIC30F2011/2012/3012/3013 devices have 2 compare channels. OCxRS and OCxR in Figure 12-1 represent the Dual Compare registers. In the Dual Compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare ...
Page 88
... Timer2 and Timer3 Selection Mode Each output compare channel can select between one of two 16-bit timers, Timer2 or Timer3. The selection of the timers is controlled by the OCTSEL bit (OCxCON<3>). Timer2 is the default timer resource for the output compare module. 12.2 Simple Output Compare Match Mode When control bits OCM< ...
Page 89
... Timer3) is enabled and the TSIDL bit of the selected timer is set to logic ‘0’. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 When the selected TMRx is equal to its respective period register, PRx, the following four events occur on the next increment cycle: • ...
Page 90
TABLE 12-1: OUTPUT COMPARE REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 OC1RS 0180 OC1R 0182 OC1CON 0184 — — OCSIDL — OC2RS 0186 OC2R 0188 OC2CON 018A — — OCSIDL — Legend: ...
Page 91
... It is useful for communicating with other peripheral devices, such as EEPROMs, shift registers, display drivers and A/D converters, or other microcontrollers compatible with Motorola's SPI and SIOP interfaces. The dsPIC30F2011/2012/3012/ 3013 devices feature one SPI module, SPI1. 13.1 Operating Function Description ...
Page 92
... Figure 13-2 depicts the a master/slave connection between two processors. In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPI1BUF. The interrupt is generated at the middle of the transfer of the last bit. In Slave mode, data is transmitted and received as external clock pulses appear on SCK ...
Page 93
... The transmitter and receiver will stop in Sleep mode. However, register contents are not affected by entering or exiting Sleep mode. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 13.5 SPI Operation During CPU Idle Mode When the device enters Idle mode, all clock sources remain functional. The SPISIDL bit (SPI1STAT< ...
Page 94
TABLE 13-1: SPI1 REGISTER MAP SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Name SPI1STAT 0220 SPIEN — SPISIDL — SPI1CON 0222 — FRMEN SPIFSD — DISSDO MODE16 SPI1BUF 0224 Note: Refer to “dsPIC30F Family Reference ...
Page 95
... Thus, the I C module can operate either as a slave master bus. FIGURE 14-1: PROGRAMMER’S MODEL Bit 15 Bit 15 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.1.1 VARIOUS I The following types • slave operation with 7-bit address 2 • slave operation with 10-bit address 2 • ...
Page 96
... FIGURE 14-2: I C™ BLOCK DIAGRAM Shift SCL Clock SDA Match Detect Stop bit Detect Stop bit Generate Shift Clock DS70139E-page 94 I2CRCV I2CRSR LSB Addr_Match I2CADD Start and Start, Restart, Collision Detect Acknowledge Generation Clock Stretching I2CTRN LSB Reload Control ...
Page 97
... SCL high. The interrupt pulse is sent on the falling edge of the ninth clock pulse, regardless of the status of the ACK received from the master. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 14.3.2 SLAVE RECEPTION If the R_W bit received is a ‘0’ during an address match, then Receive mode is initiated ...
Page 98
... MODE SLAVE TRANSMISSION Once a slave is addressed in this fashion with the full 10-bit address (we will refer to this state as “PRIOR_ADDR_MATCH”), the master can begin sending data bytes for a slave reception operation. 14.4.2 10-BIT MODE SLAVE RECEPTION Once addressed, the master can generate a Repeated ...
Page 99
... When the interrupt is serviced, the source for the inter- rupt can be checked by reading the contents of the I2CRCV to determine if the address was device specific or a general call address. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 2 14. Master Support As a master device, six operations are supported: ...
Page 100
... I C MASTER RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (I2CCON<3>). The I module must be Idle before the RCEN bit is set, other- wise the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCL pin ACK and data are shifted into the I2CRSR on the rising edge of each clock ...
Page 101
TABLE 14- REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 I2CRCV 0200 — — — — I2CTRN 0202 — — — — I2CBRG 0204 — — — — I2CCON 0206 I2CEN — ...
Page 102
... NOTES: DS70139E-page 100 © 2006 Microchip Technology Inc. ...
Page 103
... Family Reference Manual” (DS70046). This section describes the Universal Asynchronous Receiver/Transmitter Communications module. The dsPIC30F2011/2012/3012 processors have one UART module (UART1). The dsPIC30F3013 processor has two UART modules (UART1 and UART2). FIGURE 15-1: UART TRANSMITTER BLOCK DIAGRAM ...
Page 104
... FIGURE 15-2: UART RECEIVER BLOCK DIAGRAM LPBACK From UxTX 1 UxRX 0 · Start bit Detect · Parity Check · Stop bit Detect · Shift Clock Generation · Wake Logic DS70139E-page 102 Internal Data Bus 16 Read Write URX8 UxRXREG Low Byte Receive Buffer Control ...
Page 105
... The STSEL bit determines whether one or two Stop bits will be used during data transmission. The default (power-on) setting of the UART is 8 bits, no parity and 1 Stop bit (typically represented 1). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.3 Transmitting Data 15.3.1 TRANSMITTING IN 8-BIT DATA ...
Page 106
... TRANSMIT INTERRUPT The transmit interrupt flag (U1TXIF or U2TXIF) is located in the corresponding interrupt flag register. The transmitter generates an edge to set the UxTXIF bit. The condition for generating the interrupt depends on the UTXISEL control bit UTXISEL = 0, an interrupt is generated when a word is transferred from the transmit buffer to the Transmit Shift register (UxTSR) ...
Page 107
... No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has not yet been received. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 15.6 Address Detect Mode Setting the ADDEN bit (UxSTA<5>) enables this spe- cial mode in which a 9th bit (URX8) value of ‘ ...
Page 108
... Auto-Baud Support To allow the system to determine baud rates of received characters, the input can be optionally linked to a selected capture input (IC1 for UART1 and IC2 for UART2). To enable this mode, you must program the input capture module to detect the falling and rising edges of the Start bit ...
Page 109
... U2RXREG 021C — — — — — U2BRG 021E Legend uninitialized bit Note 1: UART2 is not available on the dsPIC30F2011/2012/3012 2: Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields. Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 — ALTIO — — WAKE LPBACK ...
Page 110
... NOTES: DS70139E-page 108 © 2006 Microchip Technology Inc. ...
Page 111
... AN7 1000 AN8 1001 AN9 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The ADC module has six 16-bit registers: • A/D Control Register 1 (ADCON1) • A/D Control Register 2 (ADCON2) • A/D Control Register 3 (ADCON3) • A/D Input Select Register (ADCHS) • A/D Port Configuration Register (ADPCFG) • ...
Page 112
... A/D Result Buffer The module contains a 16-word dual port read-only buffer, called ADCBUF0...ADCBUFF, to buffer the A/D results. The RAM is 12 bits wide but the data obtained is represented in one of four different 16-bit data for- mats. The contents of the sixteen A/D Conversion Result Buffer registers, ADCBUF0 through ADCBUFF, cannot be written by user software ...
Page 113
... ADC CONVERSION CLOCK (0.5*(ADCS<5:0> © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The internal RC oscillator is selected by setting the ADRC bit. For correct ADC conversions, the ADC conversion clock (T ) must be selected to ensure a minimum T AD time of 334 nsec (for V “Electrical Characteristics” for minimum T other operating conditions ...
Page 114
... Table 16-1 summa- rizes the conversion speeds for the dsPIC30F 12-bit ADC and the required operating conditions. Figure 16-2 depicts the recommended circuit for the conversion rates above 200 ksps. The dsPIC30F2011 is shown as an example. TABLE 16-1: 12-BIT ADC EXTENDED CONVERSION RATES ...
Page 115
... Note: C value depends on device package and is not tested. Effect of C PIN © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 The following figure shows the timing diagram of the ADC running at 200 ksps. The T tion with the guidelines described above allows a con- version speed of 200 ksps. See Example 16-1 for code example ...
Page 116
... Module Power-Down Modes The module has 2 internal power modes. When the ADON bit is ‘1’, the module is in Active mode fully powered and functional. When ADON is ‘0’, the module is in Off mode. The dig- ital and analog portions of the circuit are disabled for maximum current savings ...
Page 117
... ANx pins) may cause the input buffer to consume current that exceeds the device specifications. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 16.14 Connection Considerations The analog inputs have diodes to V protection. This requires that the analog input be between V DD range by greater than 0 ...
Page 118
... TABLE 16-2: A/D CONVERTER REGISTER MAP FOR dsPIC30F2011/3012 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — — — — ADCBUF4 0288 — ...
Page 119
TABLE 16-3: A/D CONVERTER REGISTER MAP FOR dsPIC30F2012/3013 SFR Addr. Bit 15 Bit 14 Bit 13 Bit 12 Name ADCBUF0 0280 — — — — ADCBUF1 0282 — — — — ADCBUF2 0284 — — — — ADCBUF3 0286 — ...
Page 120
... NOTES: DS70139E-page 118 © 2006 Microchip Technology Inc. ...
Page 121
... In the Idle mode, the clock sources are still active but the CPU is shut-off. The RC oscillator option saves system cost while the LP crystal option saves power. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.1 Oscillator System Overview The dsPIC30F oscillator system has the following modules and features: • ...
Page 122
... TABLE 17-1: OSCILLATOR OPERATING MODES Oscillator Mode XTL 200 kHz-4 MHz crystal on OSC1:OSC2 MHz-10 MHz crystal on OSC1:OSC2. XT w/PLL 4x 4 MHz-10 MHz crystal on OSC1:OSC2, 4x PLL enabled. XT w/PLL 8x 4 MHz-10 MHz crystal on OSC1:OSC2, 8x PLL enabled. XT w/PLL 16x 4 MHz-7.5 MHz crystal on OSC1:OSC2, 16x PLL enabled ...
Page 123
... OSCILLATOR SYSTEM BLOCK DIAGRAM OSC1 Primary Oscillator OSC2 Internal Fast RC Oscillator (FRC) POR Done SOSCO 32 kHz LP Oscillator SOSCI © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 F PLL PLL x4, x8, x16 PLL Lock Primary Osc Internal FRC Osc Primary Oscillator Stability Detector Oscillator Start-up ...
Page 124
... Oscillator Configurations 17.2.1 INITIAL CLOCK SOURCE SELECTION While coming out of Power-on Reset or Brown-out Reset, the device selects its clock source based on: a) FOS<2:0> Configuration bits that select one of four oscillator groups, b) and FPR<4:0> Configuration bits that select one of 15 oscillator choices within the primary group. ...
Page 125
... If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are set to ‘00001’, ‘01010’ or ‘00011’, then a PLL multiplier (respectively) is applied. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Note: When a 16x PLL is used, the FRC fre- quency must not be tuned to a frequency greater than 7.5 MHz. ...
Page 126
... FAIL-SAFE CLOCK MONITOR The Fail-Safe Clock Monitor (FSCM) allows the device to continue to operate even in the event of an oscillator failure. The FSCM function is enabled by appropriately programming the FCKSM Configuration bits (clock switch and monitor selection bits) in the FOSC Device Configuration register. If the FSCM function is enabled, ...
Page 127
... Reset state. The POR also selects the device clock source identified by the oscillator configuration fuses. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Different registers are affected in different ways by var- ious Reset conditions. Most registers are not affected by a WDT wake-up since this is viewed as the resump- tion of normal operation ...
Page 128
... FIGURE 17-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR OST TIME-OUT PWRT TIME-OUT INTERNAL Reset FIGURE 17-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ...
Page 129
... Configuration bit values (FOS<2:0> and FPR<4:0>). Furthermore Oscillator mode is © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 selected, the BOR will activate the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, then the clock will be held until the LOCK bit (OSCCON< ...
Page 130
... Table 17-5 shows the Reset conditions for the RCON register. Since the control bits within the RCON register are R/W, the information in the table means that all the bits are negated prior to the action specified in the condition column. TABLE 17-5: ...
Page 131
... In some devices, the LVD threshold voltage may be applied externally on the LVDIN pin. The LVD module is enabled by setting the LVDEN bit (RCON<12>). © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 17.6 Power-Saving Modes There are two power-saving states that can be entered through the execution of a special instruction, PWRSAV; ...
Page 132
... Any interrupt that is individually enabled (using the cor- responding IE bit) and meets the prevailing priority level will be able to wake-up the processor. The processor will process the interrupt and branch to the ISR. The Sleep Status bit in the RCON register is set upon wake-up. ...
Page 133
... Control registers are already configured to enable module operation). Note: In the dsPIC30F2011, dsPIC30F3012 and dsPIC30F2012 devices, the U2MD bit is readable and writable and will be read as ‘1’ when set. © 2006 Microchip Technology Inc. ...
Page 134
TABLE 17-7: SYSTEM INTEGRATION REGISTER MAP SFR Name Addr. Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 RCON 0740 TRAPR IOPUWR BGST LVDEN OSCCON 0742 — COSC<2:0> OSCTUN 0744 — — — — PMD1 0770 — — T3MD ...
Page 135
... The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘ ...
Page 136
... All instructions are a single word, except for certain double-word instructions, which were made double- word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. ...
Page 137
... Y data space prefetch address register for DSP instructions {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Wyd Y data space prefetch destination register for DSP instructions © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description {W0..W15} { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } {W0..W15} {W0..W15} {W0..W15} { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } {W4 ...
Page 138
... TABLE 18-2: INSTRUCTION SET OVERVIEW Base Assembly Instr Assembly Syntax Mnemonic # 1 ADD ADD Acc ADD f ADD f,WREG ADD #lit10,Wn ADD Wb,Ws,Wd ADD Wb,#lit5,Wd ADD Wso,#Slit4,Acc 2 ADDC ADDC f ADDC f,WREG ADDC #lit10,Wn ADDC Wb,Ws,Wd ADDC Wb,#lit5,Wd 3 AND AND f AND f,WREG ...
Page 139
... DEC2 f DEC2 f,WREG DEC2 Ws,Wd 28 DISI DISI #lit14 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Bit Test Bit Test Ws< ...
Page 140
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 29 DIV DIV.S Wm,Wn DIV.SD Wm,Wn DIV.U Wm,Wn DIV.UD Wm,Wn 30 DIVF DIVF Wm, #lit14,Expr DO Wn,Expr Wm*Wm,Acc,Wx,Wy,Wxd 33 EDAC EDAC Wm*Wm,Acc,Wx,Wy,Wxd 34 EXCH EXCH Wns,Wnd 35 FBCL FBCL Ws,Wnd 36 FF1L FF1L Ws,Wnd 37 FF1R FF1R ...
Page 141
... RRC RRC f RRC f,WREG RRC Ws,Wd © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Description Multiply Accumulator Square Wm to Accumulator -(Multiply Wm by Wn) to Accumulator Multiply and Subtract from Accumulator {Wnd+1, Wnd} = signed(Wb) * signed(Ws) {Wnd+1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd+1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd+1, Wnd} = unsigned(Wb) * ...
Page 142
... TABLE 18-2: INSTRUCTION SET OVERVIEW (CONTINUED) Base Assembly Instr Assembly Syntax Mnemonic # 66 RRNC RRNC f RRNC f,WREG RRNC Ws,Wd 67 SAC SAC Acc,#Slit4,Wdo SAC.R Acc,#Slit4,Wdo Ws,Wnd 69 SETM SETM f SETM WREG SETM Ws 70 SFTAC SFTAC Acc,Wn SFTAC Acc,#Slit6 f,WREG SL Ws,Wd ...
Page 143
... MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit micro- controller market ...
Page 144
... MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging ...
Page 145
... The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 19.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD powerful, low-cost, connecting to the host PC via an RS-232 or high-speed USB interface ...
Page 146
... PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages pins. ...
Page 147
... Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 (except V and MCLR) (Note 1) .................................... -0. .......................................................................................................... ± > ...................................................................................................± pin, inducing currents greater than 80 mA, may cause latch-up. ...
Page 148
... TABLE 20-2: THERMAL OPERATING CONDITIONS Rating dsPIC30F201x-30I dsPIC30F301x-30I Operating Junction Temperature Range Operating Ambient Temperature Range dsPIC30F201x-20E dsPIC30F301x-20E Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: ∑ – I INT I/O Pin power dissipation ∑ ...
Page 149
... All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data DD Memory are operational. No peripheral modules are operating. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C ...
Page 150
... TABLE 20-6: DC CHARACTERISTICS: IDLE CURRENT (I DC CHARACTERISTICS Parameter (1) Typical Max No. (2) Operating Current ( DC51a 1.3 2.5 DC51b 1.3 2.5 DC51c 1.2 2.5 DC51e 3.2 5.0 DC51f 2.9 5.0 DC51g 2.8 5.0 DC50a 3.0 5.0 DC50b 3.0 5.0 DC50c 3.0 5.0 DC50e 6 ...
Page 151
... LVD, BOR, WDT, etc. are all switched off. 3: The current is the additional current consumed when the module is enabled. This current should be added to the base I current. PD © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T Units A 25° ...
Page 152
... TABLE 20-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS DC CHARACTERISTICS Param Symbol Characteristic No. V Input Low Voltage IL DI10 I/O pins: with Schmitt Trigger buffer DI15 MCLR DI16 OSC1 (in XT, HS and LP modes) DI17 OSC1 (in RC mode) DI18 SDA, SCL DI19 SDA, SCL V Input High Voltage ...
Page 153
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature (1) ...
Page 154
... FIGURE 20-1: LOW-VOLTAGE DETECT CHARACTERISTICS V DD LV10 LVDIF (LVDIF set by hardware) TABLE 20-10: ELECTRICAL CHARACTERISTICS: LVDL DC CHARACTERISTICS Param Symbol Characteristic No. LV10 V LVDL Voltage on V PLVD high-to-low LV15 V External LVD input pin LVDIN threshold voltage Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 155
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: These parameters are characterized but not tested in manufacturing values not in usable operating range. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 BO15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C T ...
Page 156
... TABLE 20-12: DC CHARACTERISTICS: PROGRAM AND EEPROM DC CHARACTERISTICS Param Symbol Characteristic No. Data EEPROM Memory D120 E Byte Endurance D D121 V V for Read/Write DRW DD D122 T Erase/Write Cycle Time DEW D123 T Characteristic Retention RETD D124 I I During Programming DEW DD Program Flash Memory D130 E Cell Endurance ...
Page 157
... Load Condition 1 — for all pins except OSC2 Pin FIGURE 20-4: EXTERNAL CLOCK TIMING Q4 OSC1 CLKO © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T Operating voltage V range as described in Section 20.0 “Electrical DD Characteristics” ...
Page 158
... TABLE 20-14: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OS10 F External CLKN Frequency OSC (External clocks allowed only in EC mode) Oscillator Frequency OS20 1/F OSC OSC OSC OS25 T Instruction Cycle Time CY (2) OS30 TosL, External Clock in (OSC1) TosH High or Low Time ...
Page 159
... Operating temperature Param Characteristic No. OS61 x4 PLL x8 PLL x16 PLL Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 = 2 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C T (1) (2) Min ...
Page 160
... TABLE 20-17: INTERNAL CLOCK TIMING EXAMPLES Clock F OSC Oscillator T CY (1) (MHz) Mode EC 0.200 Note 1: Assumption: Oscillator Postscaler is divide Instruction Execution Cycle Time Instruction Execution Frequency: MIPS = (F cycle]. DS70139E-page 158 (3) (3) MIPS MIPS (2) ( sec) w/o PLL w PLL x4 20.0 0.05 — 1.0 1 ...
Page 161
... Overall FRC variation can be calculated by adding the absolute values of jitter, accuracy and drift percentages. TABLE 20-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param Characteristic No. (1) LPRC @ Freq. = 512 kHz OS65 Note 1: Change of LPRC frequency as V © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 -40°C T -40°C T Min Typ Max Units (1) — +0.04 +0.16 % -40° ...
Page 162
... FIGURE 20-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) I/O Pin Old Value (Output) Note: Refer to Figure 20-3 for load conditions. TABLE 20-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. DO31 T R Port output rise time IO DO32 ...
Page 163
... Data in “Typ” column is at 5V, 25°C unless otherwise stated. 3: Refer to Figure 20-2 and Table 20-11 for BOR. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SY10 SY13 Note: Refer to Figure 20-3 for load conditions. Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) ...
Page 164
... FIGURE 20-7: BAND GAP START-UP TIME CHARACTERISTICS 0V Enable Band Gap (see Note) Note: Set LVDEN bit (RCON<12>) or FBORPOR<7>set. TABLE 20-22: BAND GAP START-UP TIME REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. SY40 T Band Gap Start-up Time BGAP Note 1: These parameters are characterized but not tested in manufacturing. ...
Page 165
... TCS (T1CON, bit 1)) TA20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer1 is a Type A. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Tx11 Tx10 Tx15 OS60 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature Min Typ Synchronous, 0 ...
Page 166
... TABLE 20-24: TYPE B TIMER (TIMER2 AND TIMER4) EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TtxH TB10 TxCK High Time TB11 TtxL TxCK Low Time TB15 TtxP TxCK Input Period Synchronous, TB20 T Delay from External TxCK Clock CKEXTMRL Edge to Timer Increment Note: Timer2 and Timer4 are Type B ...
Page 167
... TccH ICx Input High Time IC15 TccP ICx Input Period Note 1: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IC10 IC11 IC15 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C T -40°C ...
Page 168
... FIGURE 20-10: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) Note: Refer to Figure 20-3 for load conditions. TABLE 20-27: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. OC10 TccF OCx Output Fall Time OC11 TccR OCx Output Rise Time Note 1: These parameters are characterized but not tested in manufacturing ...
Page 169
... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 OC20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature ...
Page 170
... FIGURE 20-12: SPI MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SDOx SP31 SDIx MSb IN SP40 SP41 Note: Refer to Figure 20-3 for load conditions. TABLE 20-29: SPI MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP10 SP21 SP35 SP20 BIT LSb BIT LSb IN Note: Refer to Figure 20-3 for load conditions ...
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... FIGURE 20-14: SPI MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS SS X SP50 SCK X (CKP = 0) SP71 SCK X (CKP = 1) SP35 SDO X SDI SDI X SP40 Note: Refer to Figure 20-3 for load conditions. TABLE 20-31: SPI MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No ...
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... SCK X (CKP = 0) SP71 SCK X (CKP = 1) MSb SDO X SDI SDI X MSb IN SP41 SP40 Note: Refer to Figure 20-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 SP70 SP73 SP35 SP72 SP52 BIT LSb SP30,SP31 BIT LSb IN SP52 SP72 SP73 SP51 DS70139E-page 171 ...
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... TABLE 20-32: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol Characteristic No. TscL SP70 SCK Input Low Time X SP71 TscH SCK Input High Time X SP72 TscF SCK Input Fall Time X SP73 TscR SCK Input Rise Time X SP30 TdoF SDO ...
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... I C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 SCL IM11 IM10 SDA In IM40 SDA Out Note: Refer to Figure 20-3 for load conditions. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IM11 IM10 IM26 IM25 IM40 IM34 IM33 Stop Condition IM21 IM33 IM45 ...
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... I TABLE 20-33: I C™ BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param Symbol Characteristic No. IM10 T : Clock Low Time 100 kHz mode LO SCL 400 kHz mode 1 MHz mode IM11 T : Clock High Time 100 kHz mode HI SCL 400 kHz mode 1 MHz mode ...
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... F SCL Fall Time IS21 T : SDA and SCL R SCL Rise Time Note 1: Maximum pin capacitance = 10 pF for all I © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 IS11 IS10 IS26 IS25 IS40 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° -40° Min ...
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... TABLE 20-34: C™ BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED CHARACTERISTICS Param Symbol Characteristic No. IS25 T : Data Input SU DAT Setup Time IS26 T : Data Input HD DAT Hold Time IS30 T : Start Condition SU STA Setup Time IS31 T : Start Condition HD STA Hold Time IS33 T : Stop Condition ...
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... These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 CA10 CA11 CA20 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40° ...
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... TABLE 20-36: 12-BIT ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param Symbol Characteristic No. AD01 AV Module V Supply DD DD AD02 AV Module V Supply SS SS AD05 V Reference Voltage High REFH AD06 V Reference Voltage Low REFL AD07 V Absolute Reference REF Voltage AD08 I Current Drain REF AD10 V -V Full-Scale Input Span ...
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... Effective Number of Bits Note 1: The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. 2: Measurements taken with external V © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C -40°C Min. ...
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... FIGURE 20-21: 12-BIT A/D CONVERSION TIMING CHARACTERISTICS (ASAM = 0, SSRC = 000) AD50 ADCLK Instruction Set SAMP Clear SAMP Execution SAMP ch0_dischrg ch0_samp eoc AD61 AD60 T SAMP DONE ADIF ADRES( Software sets ADCON. SAMP to start sampling Sampling starts after discharge period described in the “dsPIC30F Family Reference Manual”, (DS70046), Section 18. ...
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... Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. 2: These parameters are characterized but not tested in manufacturing. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Standard Operating Conditions: 2.7V to 5.5V (unless otherwise stated) TABLE 20-38: OPERATING TEMPERATURE-40° -40° ...
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... NOTES: DS70139E-page 182 © 2006 Microchip Technology Inc. ...
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... In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Example dsPIC30F3012 30I/P Example dsPIC30F2011 30I/SO e 0610017 Example dsPIC30F2012 30I/ ...
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... Package Marking Information (Continued) 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXX XXXXXXX YYWWNNN 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN DS70139E-page 184 Example dsPIC30F3013 e 30I/SO 3 0610017 Example 30F2011 30I/ 0610017 Example dsPIC 30F3013 30I/ 0610017 © 2006 Microchip Technology Inc. ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* MIN ...
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... Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width ...
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... Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 Units INCHES* MIN ...
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... Plastic Small Outline (SO) – Wide, 300 mil Body (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width ...
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... Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Package is saw singulated 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 EXPOSED PAD ...
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... Plastic Quad Flat, No Lead Package (ML) - 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D TOP VIEW A3 Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width ...
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... I/O pin Input Specifications (see Table 20-8) • BOR voltage limits (see Table 20-11) • Watchdog Timer time-out limits (see Table 20-21) Revision E (December 2006) This revision includes updates to the packaging diagrams. © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 191 ...
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... NOTES: DS70139E-page 192 © 2006 Microchip Technology Inc. ...
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... Implementation ........................................................... 44 Modifier Values Table ................................................. 45 Sequence Table (16-Entry)......................................... 45 Block Diagrams 12-bit ADC Functional............................................... 109 16-bit Timer1 Module .................................................. 71 16-bit Timer2............................................................... 77 16-bit Timer3............................................................... 77 32-bit Timer2/3............................................................ 76 DSP Engine ................................................................ 22 dsPIC30F2011 ............................................................ 10 dsPIC30F2012 ............................................................ 11 dsPIC30F3013 ............................................................ 13 External Power-on Reset Circuit............................... 127 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 .............................................................................. 94 Input Capture Mode.................................................... 81 Oscillator System ...
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... Erasing, Block ............................................................. 54 Erasing, Word ............................................................. 54 Protection Against Spurious Write .............................. 56 Reading....................................................................... 53 Write Verify ................................................................. 56 Writing ......................................................................... 55 Writing, Block .............................................................. 55 Writing, Word .............................................................. 55 DC Characteristics ............................................................ 145 BOR .......................................................................... 153 Brown-out Reset ....................................................... 153 I/O Pin Input Specifications ....................................... 151 I/O Pin Output Specifications .................................... 151 Idle Current (I ) .................................................... 148 IDLE Low-Voltage Detect................................................... 152 LVDL ...
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... Port Write/Read Example ................................................... 58 PORTB Register Map for dsPIC30F2011/3012 ....................... 59 Register Map for dsPIC30F2012/3013 ....................... 59 PORTC Register Map for dsPIC30F2011/2012/3012/3013 ..... 59 PORTD Register Map for dsPIC30F2011/3012 ....................... 59 Register Map for dsPIC30F2012/3013 ....................... 60 PORTF Register Map for dsPIC30F2012/3013 ....................... 60 Power Saving Modes........................................................ 129 Idle............................................................................ 130 Sleep ........................................................................ 129 Sleep and Idle........................................................... 119 ...
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... Power-on Reset (POR) ............................................. 119 Power-up Timer (PWRT) .......................................... 119 Reset Sequence.................................................................. 65 Reset Sources ............................................................ 65 Reset Sources Brown-out Reset (BOR) .............................................. 65 Illegal Instruction Trap................................................. 65 Trap Lockout ............................................................... 65 Uninitialized W Register Trap ..................................... 65 Watchdog Time-out..................................................... 65 Reset Timing Characteristics ............................................ 161 Reset Timing Requirements.............................................. 161 Run-Time Self-Programming (RTSP) ................................. 47 S Simple Capture Event Mode ............................................... 81 Buffer Operation ...
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... Wake-up from Sleep ......................................................... 119 Wake-up from Sleep and Idle ............................................. 68 Watchdog Timer Timing Characteristics .............................................. 161 Timing Requirements................................................ 161 Watchdog Timer (WDT) ............................................ 119, 129 Enabling and Disabling ............................................. 129 Operation .................................................................. 129 WWW Address.................................................................. 199 WWW, On-Line Support ....................................................... 7 © 2006 Microchip Technology Inc. dsPIC30F2011/2012/3012/3013 DS70139E-page 197 ...
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... DS70139E-page 198 © 2006 Microchip Technology Inc. ...