PIC18LF2321-I/SS Microchip Technology, PIC18LF2321-I/SS Datasheet - Page 259
![IC PIC MCU FLASH 4KX16 28SSOP](/photos/6/81/68119/150-28-ssop_sml.jpg)
PIC18LF2321-I/SS
Manufacturer Part Number
PIC18LF2321-I/SS
Description
IC PIC MCU FLASH 4KX16 28SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(402 pages)
3.PIC18F2221-ISO.pdf
(8 pages)
4.PIC18F2221-ISO.pdf
(30 pages)
5.PIC18F2221-ISO.pdf
(46 pages)
6.PIC18F2321-IML.pdf
(396 pages)
Specifications of PIC18LF2321-I/SS
Core Size
8-Bit
Program Memory Size
8KB (4K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
25
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 10x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
40MHz
No. Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F2221-ISO PDF datasheet #3
- PIC18F2221-ISO PDF datasheet #4
- PIC18F2221-ISO PDF datasheet #5
- PIC18F2321-IML PDF datasheet #6
- Current page: 259 of 402
- Download datasheet (7Mb)
24.0
PIC18F2221/2321/4221/4321 family devices include
several features intended to maximize reliability and
minimize
components. These are:
• Oscillator Selection
• Resets:
• Interrupts
• Watchdog Timer (WDT)
• Fail-Safe Clock Monitor
• Two-Speed Start-up
• Code Protection
• ID Locations
• In-Circuit Serial Programming
The oscillator can be configured for the application
depending on frequency, power, accuracy and cost. All
of the options are discussed in detail in Section 3.0
“Oscillator Configurations”.
A complete discussion of device Resets and interrupts
is available in previous sections of this data sheet.
In addition to their Power-up and Oscillator Start-up
Timers provided for Resets, PIC18F2221/2321/4221/
4321 family devices have a Watchdog Timer, which is
either permanently enabled via the Configuration bits
or software controlled (if configured as disabled).
TABLE 24-1:
© 2009 Microchip Technology Inc.
300001h
300002h
300003h
300005h
300006h
300008h
300009h
30000Ah
30000Bh
30000Ch
30000Dh
3FFFFEh DEVID1
3FFFFFh DEVID2
Legend:
Note 1:
- Power-on Reset (POR)
- Power-up Timer (PWRT)
- Oscillator Start-up Timer (OST)
- Brown-out Reset (BOR)
File Name
2:
SPECIAL FEATURES OF THE
CPU
CONFIG1H
CONFIG2L
CONFIG2H
CONFIG3H MCLRE
CONFIG4L
CONFIG5L
CONFIG5H
CONFIG6L
CONFIG6H
CONFIG7L
CONFIG7H
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved, maintain as ‘0’.
Shaded cells are unimplemented, read as ‘0’.
Unimplemented in PIC18F2221/4221 devices; maintain these bits set.
See Register 24-14 for DEVID1 values. DEVID registers are read-only and cannot be programmed by the user.
cost
CONFIGURATION BITS AND DEVICE IDs
through
(1)
(1)
PIC18F2221/2321/4221/4321 FAMILY
DEBUG
DEV10
WRTD
DEV2
IESO
Bit 7
CPD
—
—
—
—
—
—
elimination
FCMEN
EBTRB
XINST
WRTB
DEV1
DEV9
Bit 6
CPB
—
—
—
—
—
—
of
BBSIZ1
WRTC
DEV0
DEV8
Bit 5
—
—
—
—
—
—
—
—
—
external
WDTPS3 WDTPS2 WDTPS1 WDTPS0
BORV1
BBSIZ0
REV4
DEV7
Bit 4
—
—
—
—
—
—
—
—
FOSC3
BORV0
REV3
DEV6
The inclusion of an internal RC oscillator also provides
the additional benefits of a Fail-Safe Clock Monitor
(FSCM) and Two-Speed Start-up. FSCM provides for
background monitoring of the peripheral clock and
automatic switchover in the event of its failure. Two-
Speed Start-up enables code to be executed almost
immediately on start-up, while the primary clock source
completes its start-up delays.
All of these features are enabled and configured by
setting the appropriate Configuration register bits.
24.1
The Configuration bits can be programmed (read as
‘0’) or left unprogrammed (read as ‘1’) to select various
device configurations. These bits are mapped starting
at program memory location 300000h.
The user will note that address 300000h is beyond the
user program memory space. In fact, it belongs to the
configuration memory space (300000h-3FFFFFh), which
can only be accessed using table reads and table writes.
Programming the Configuration registers is done in a
manner similar to programming the Flash memory. The
WR bit in the EECON1 register starts a self-timed write
to the Configuration register. In normal operation mode,
a TBLWT instruction with the TBLPTR pointing to the
Configuration register sets up the address and the data
for the Configuration register write. Setting the WR bit
starts a long write to the Configuration register. The
Configuration registers are written a byte at a time. To
write or erase a configuration cell, a TBLWT instruction
can write a ‘1’ or a ‘0’ into the cell. For additional details
on Flash programming, refer to Section 7.5 “Writing
to Flash Program Memory”.
Bit 3
—
—
—
—
—
—
—
r
LPT1OSC PBADEN CCP2MX
BOREN1 BOREN0 PWRTEN
Configuration Bits
FOSC2
REV2
DEV5
Bit 2
LVP
—
—
—
—
—
—
FOSC1
EBTR1
WRT1
REV1
DEV4
Bit 1
CP1
—
—
—
—
STVREN
WDTEN
FOSC0
EBTR0
WRT0
REV0
DEV3
Bit 0
CP0
—
—
—
DS39689F-page 259
Unprogrammed
00-- 0111
---1 1111
---1 1111
1--- -011
1000 01-1
---- --11
11-- ----
---- --11
111- ----
---- --11
-1-- ----
xxxx xxxx
0000 1100
Default/
Value
(2)
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