PIC16CE624-04/P Microchip Technology, PIC16CE624-04/P Datasheet - Page 10

• Manufacturer Part Number: PIC16CE624-04/P
• Description: IC MCU OTP 1KX14 EE COMP 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16CE624-04/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Oscillator Type: External
• Core Processor: PIC
• Speed: 4MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 13
• Program Memory Type: OTP
• Eeprom Size: 128 x 8
• Ram Size: 96 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 18-DIP (0.300", 7.62mm)
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 96Byte
• Cpu Speed: 4MHz
• No. Of: RoHS Compliant
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 96 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 1
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1059 - ADAPTER 18 ZIF BD W/18SO PLUGSDVA16XP180 - ADAPTER DEVICE FOR MPLAB-ICEAC164010 - MODULE SKT PROMATEII DIP/SOIC
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16CE62X
3.1
The clock input (OSC1/CLKIN pin) is internally divided
by four to generate four non-overlapping quadrature
clocks namely Q1, Q2, Q3 and Q4. Internally, the
program counter (PC) is incremented every Q1, the
instruction is fetched from the program memory and
latched into the instruction register in Q4. The
instruction is decoded and executed during the
following Q1 through Q4. The clocks and instruction
execution flow is shown in Figure 3-2.
FIGURE 3-2:
EXAMPLE 3-1:
DS40182C-page 10
1. MOVLW 55h
2. MOVWF PORTB
3. CALL
4. BSF
5. Instruction @
All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed”
from the pipeline, while the new instruction is being fetched and then executed.
address SUB_1
OSC2/CLKOUT
Clocking Scheme/Instruction Cycle
(RC mode)
SUB_1
PORTA, BIT3
OSC1
CLOCK/INSTRUCTION CYCLE
Q4
PC
Q2
Q3
Q1
INSTRUCTION PIPELINE FLOW
Q1
Execute INST (PC-1)
Fetch INST (PC)
Fetch 1
Q2
PC
Q3
Execute 1
Fetch 2
Q4
Q1
Execute INST (PC)
Execute 2
Fetch INST (PC+1)
Fetch 3
Q2
PC+1
3.2
An “Instruction Cycle” consists of four Q cycles (Q1,
Q2, Q3 and Q4). The instruction fetch and execute are
pipelined such that fetch takes one instruction cycle,
while decode and execute takes another instruction
cycle. However, due to the pipelining, each instruction
effectively executes in one cycle. If an instruction
causes the program counter to change (i.e., GOTO) then
two cycles are required to complete the instruction
(Example 3-1).
A fetch cycle begins with the program counter (PC)
incrementing in Q1.
In the execution cycle, the fetched instruction is latched
into the “Instruction Register (IR)” in cycle Q1. This
instruction is then decoded and executed during the
Q2, Q3, and Q4 cycles. Data memory is read during Q2
(operand read) and written during Q4 (destination
write).
Q3
Execute 3
Fetch 4
Instruction Flow/Pipelining
Q4
Q1
Fetch SUB_1
Execute INST (PC+1)
Fetch INST (PC+2)
Q2
Flush
1999 Microchip Technology Inc.
PC+2
Q3
Execute SUB_1
Q4
Internal
phase
clock