PIC12F615-I/MD Microchip Technology, PIC12F615-I/MD Datasheet - Page 36

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PIC12F615-I/MD

Manufacturer Part Number
PIC12F615-I/MD
Description
IC PIC MCU FLASH 1KX14 8DFN
Manufacturer
Microchip Technology
Series
PIC® 12Fr

Specifications of PIC12F615-I/MD

Core Size
8-Bit
Program Memory Size
1.75KB (1K x 14)
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Program Memory Type
FLASH
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DFN
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
64Byte
Cpu Speed
20MHz
No. Of Timers
3
Digital Ic Case Style
DFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
APGRD004 - REF DESIGN MOD AUTO AMBNT LIGHTAC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC164326 - MODULA SKT PM3 20QFNXLT08DFN2 - SOCKET TRANSITION ICE 14DIP/8DFN
Eeprom Size
-
Connectivity
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
PIC12F609/615/12HV609/615
REGISTER 4-5:
REGISTER 4-6:
DS41302A-page 34
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-4
bit 3
bit 2-0
Note 1:
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7-6
bit 5-0
Note 1:
U-0
U-0
2:
3:
4:
2:
Global GPPU must be enabled for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is in Output mode (TRISIO = 0).
The GP3 pull-up is enabled when configured as MCLR and disabled as an I/O in the Configuration Word.
WPU<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Global Interrupt Enable (GIE) must be enabled for individual interrupts to be recognized.
IOC<5:4> always reads ‘1’ in XT, HS and LP Oscillator modes.
Unimplemented: Read as ‘0’
WPU<5:4>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
WPU<2:0>: Weak Pull-up Control bits
1 = Pull-up enabled
0 = Pull-up disabled
Unimplemented: Read as ‘0’
IOC<5:0>: Interrupt-on-change GPIO Control bit
1 = Interrupt-on-change enabled
0 = Interrupt-on-change disabled
U-0
U-0
WPU: WEAK PULL-UP GPIO REGISTER
IOC: INTERRUPT-ON-CHANGE GPIO REGISTER
W = Writable bit
‘1’ = Bit is set
W = Writable bit
‘1’ = Bit is set
R/W-1
WPU5
R/W-0
IOC5
WPU4
R/W-1
R/W-0
IOC4
Preliminary
U = Unimplemented bit, read as ‘0’
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
‘0’ = Bit is cleared
R/W-0
IOC3
U-0
R/W-1
WPU2
R/W-0
IOC2
© 2006 Microchip Technology Inc.
x = Bit is unknown
x = Bit is unknown
WPU1
R/W-1
R/W-0
IOC1
WPU0
R/W-1
R/W-0
IOC0
bit 0
bit 0

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