SAK-C167CS-LM CA+ Infineon Technologies, SAK-C167CS-LM CA+ Datasheet - Page 69

• Manufacturer Part Number: SAK-C167CS-LM CA+
• Description: IC MCU 16BIT 25MHZ MQFP-144
• Manufacturer: Infineon Technologies
• Series: C16xxr

Specifications of SAK-C167CS-LM CA+

• Core Processor: C166
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: CAN, EBI/EMI, SPI, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Type: ROMless
• Ram Size: 11K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144- BSQFP
• Packages: PG-MQFP-144
• Max Clock Frequency: 25.0 MHz
• Sram (incl. Cache): 11.0 KByte
• Can Nodes: 2
• A / D Input Lines (incl. Fadc): 24
• Program Memory: 0.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: K167CSLMCAZNP; K167CSLMCAZXP; K167CSLMCAZXT; SAK-C167CS-LM CA+; SAK-C167CS-LMCAIN; SAKC167CSLMCAT; SP000103492

The bandwidth of a parameter (minimum and maximum value) covers the whole
operating range (temperature, voltage) as well as process variations. Within a given
device, however, this bandwidth is smaller than the specified range. This is also due to
interdependencies between certain parameters. Some of these interdependencies are
described as relative timing (see below) or in additional notes (see standard timing).
Table 18
Parameter
Output hold time after WR rising edge
Valid for: address, write data out
Input hold time after RD rising edge
Valid for: read data in
1)
2)
General Notes For The Following Bus Timing Figures
These standard notes apply to all subsequent timing figures. Additional individual notes
are placed at the respective figure.
1)
2)
3)
4)
Data Sheet
Not 100% tested, guaranteed by design and characterization.
See also note
The falling edge of signals RD and WR/WRH/WRL/WrCS is controlled by the Read/Write delay feature
(bit BUSCON.RWDCx).
The rising edge of signal WR/WRH/WRL/WrCS is controlled by the early write feature (bit BUSCON.EWENx).
A bus cycle is extended here, if MCTC waitstates are selected or if the READY input is sampled inactive.
A bus cycle is extended here, if an MTTC waitstate is selected.
3)
External Bus Relative Timing (Operating Conditions apply)
in
Table
17.
2)
65
Symbol
t
t
50
51
CC 0
SR –
min.
Limits
max.
–
0
C167CS-4R
V2.2, 2001-08
1)
C167CS-L
Unit
ns
ns