SAK-XC2267-96F66L AC Infineon Technologies, SAK-XC2267-96F66L AC Datasheet - Page 106
SAK-XC2267-96F66L AC
Manufacturer Part Number
SAK-XC2267-96F66L AC
Description
IC MCU 16BIT FLASH PG-LQFP-100
Manufacturer
Infineon Technologies
Series
XC22xxr
Datasheet
1.SAK-XC2264-56F66L_AC.pdf
(116 pages)
Specifications of SAK-XC2267-96F66L AC
Core Processor
C166SV2
Core Size
16/32-Bit
Speed
66MHz
Connectivity
CAN, EBI/EMI, I²C, LIN, SPI, SSC, UART/USART, USI
Peripherals
DMA, I²S, POR, PWM, WDT
Number Of I /o
75
Program Memory Size
768KB (768K x 8)
Program Memory Type
FLASH
Ram Size
82K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x8/10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-LFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
KX226796F66L82ACXT
SAK-XC2267-96F66L82 AC
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66LACINTR
SP000250942
SAK-XC2267-96F66L82 AC
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66L82ACINTR
SAK-XC2267-96F66LACINTR
SP000250942
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XC2267 / XC2264
XC2000 Family Derivatives
Electrical Parameters
Bus Cycle Control with the READY Input
The duration of an external bus cycle can be controlled by the external circuit using the
READY input signal. The polarity of this input signal can be selected.
Synchronous READY permits the shortest possible bus cycle but requires the input
signal to be synchronous to the reference signal CLKOUT.
An asynchronous READY signal puts no timing constraints on the input signal but incurs
a minimum of one waitstate due to the additional synchronization stage. The minimum
duration of an asynchronous READY signal for safe synchronization is one CLKOUT
period plus the input setup time.
An active READY signal can be deactivated in response to the trailing (rising) edge of
the corresponding command (RD or WR).
If the next bus cycle is controlled by READY, an active READY signal must be disabled
before the first valid sample point in the next bus cycle. This sample point depends on
the programmed phases of the next cycle.
Data Sheet
104
V2.1, 2008-08
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