SAF-XC164TM-4F40F AA Infineon Technologies, SAF-XC164TM-4F40F AA Datasheet - Page 61

• Manufacturer Part Number: SAF-XC164TM-4F40F AA
• Description: IC MCU 16BIT 32KB TQFP-64-8
• Manufacturer: Infineon Technologies
• Series: XC16xr

Specifications of SAF-XC164TM-4F40F AA

• Core Processor: C166SV2
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: SPI, UART/USART
• Peripherals: PWM, WDT
• Number Of I /o: 47
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 2.7 V
• Data Converters: A/D 14x8/10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LFQFP
• Packages: PG-LQFP-64
• Max Clock Frequency: 40.0 MHz
• Sram (incl. Cache): 4.0 KByte
• A / D Input Lines (incl. Fadc): 14
• Program Memory: 32.0 KByte
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Other names: FX164TM4F40FAAXT; SAF-XC164TM-4F40FAA; SAF-XC164TM-4F40FAAINTR; SAF-XC164TM-4F40FAATR; SAF-XC164TM-4F40FAATR; SAFXC164TM4F40FAAXT; SP000105871

4.4.2
The XC164TM’s Flash module delivers data within a fixed access time (see
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time
frequency.
The Flash access waitstates only affect non-sequential accesses. Due to prefetching
mechanisms, the performance for sequential accesses (depending on the software
structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average performance by
5% … 15%.
Table 17
Parameter
Flash module access time
Programming time per 128-byte block
Erase time per sector
1) The actual access time is influenced by the system frequency, see
2) Programming and erase time depends on the system frequency. Typical values are valid for 40 MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 18
Table 18
Required Waitstates
0 WS (WSFLASH = 00
1 WS (WSFLASH = 01
Note: The maximum achievable system frequency is limited by the properties of the
Data Sheet
t
ACC
respective derivative, i.e. 40 MHz (or 20 MHz for XC164TM-xF20F devices).
of the Flash array. The required Flash waitstates depend on the actual system
indicates the interrelation of waitstates and system frequency.
On-chip Flash Operation
Flash Characteristics (Operating Conditions apply)
Flash Access Waitstates
B
B
)
)
Symbol
t
t
t
ACC
PR
ER
Frequency Range
f
f
CPU
CPU
59
≤ 20 MHz
≤ 40 MHz
CC –
CC –
CC –
Min.
Table
Limit Values
18.
Typ.
–
2
200
2)
Electrical Parameters
2)
Max.
50
5
500
1)
Derivatives
V1.2, 2007-03
XC164TM
Table
Unit
ns
ms
ms
17).