AT90USB162-16MUR Atmel, AT90USB162-16MUR Datasheet - Page 205
AT90USB162-16MUR
Manufacturer Part Number
AT90USB162-16MUR
Description
IC AVR MCU 16K FLASH 32QFN
Manufacturer
Atmel
Series
AVR® 90USBr
Datasheet
1.AT90USB82-16MU.pdf
(307 pages)
Specifications of AT90USB162-16MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
EBI/EMI, PS/2, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFN
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART, debugWIRE
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATSTK526 - KIT STARTER FOR AT90USB82/162ATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVRATSTK525 - KIT STARTER FOR AT90USBAT90USBKEY2 - KIT DEMO FOR AT90USB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
AT90USB162-16MURTR
AT90USB162-16MUTR
AT90USB162-16MUTR
AT90USB162-16MUTR
AT90USB162-16MUTR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT90USB162-16MUR
Manufacturer:
TT
Quantity:
400 000
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20.14.1
20.14.1.1
7707F–AVR–11/10
Example with 1 IN data bank
Detailed description
Example with 2 IN data banks
FIFOCON
FIFOCON
TXINI
TXINI
Abort
SW
SW
write data from CPU
write data from CPU
The RWAL bit always reflects the state of the current bank. This bit is set if the firmware can
write data to the bank, and cleared by hardware when the bank is full.
The data are written by the CPU, following the next flow:
If the endpoint uses 2 banks, the second one can be read by the HOST while the current is
being written by the CPU. Then, when the CPU clears FIFOCON, the next bank may be already
ready (free) and TXINI is set immediately.
An “abort” stage can be produced by the host in some situations:
• When the bank is empty, an endpoint interrupt (EPINTx) is triggered, if enabled (TXINE set)
• The CPU acknowledges the interrupt by clearing TXINI,
• The CPU can write the data into the current bank (write in UEDATX),
• The CPU can free the bank by clearing FIFOCON when all the data are written, that is:
• after “N” write into UEDATX
• as soon as RWAL is cleared by hardware.
NAK
BANK 0
and TXINI is set. The CPU can also poll TXINI or FIFOCON, depending the software
architecture choice,
BANK 0
SW
SW
IN
IN
SW
write data from CPU
BANK 1
(bank 0)
(bank 0)
DATA
DATA
SW
HW
HW
ACK
ACK
SW
SW
write data from CPU
write data from CPU
IN
BANK 0
BANK0
AT90USB82/162
(bank 1)
DATA
SW
IN
ACK
205
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