MC68332ACEH20 Freescale Semiconductor, MC68332ACEH20 Datasheet - Page 130
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MC68332ACEH20
Manufacturer Part Number
MC68332ACEH20
Description
IC MCU 32BIT 20MHZ 132-PQFP
Manufacturer
Freescale Semiconductor
Series
M683xxr
Specifications of MC68332ACEH20
Core Processor
CPU32
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
15
Program Memory Type
ROMless
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
132-QFP
Processor Series
M683xx
Core
CPU32
Data Bus Width
32 bit
Maximum Clock Frequency
20 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Interface Type
SCI, SPI, UART
Minimum Operating Temperature
- 40 C
Controller Family/series
68K
No. Of I/o's
15
Ram Memory Size
2KB
Cpu Speed
20MHz
No. Of Timers
1
Embedded Interface Type
QSPI, SCI, UART
Digital Ic Case Style
PQFP
Rohs Compliant
Yes
Data Ram Size
2 KB
Number Of Programmable I/os
15
Number Of Timers
16
Cpu Family
68K/M683xx
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
20MHz
Program Memory Size
Not Required
Total Internal Ram Size
2KB
# I/os (max)
15
Number Of Timers - General Purpose
16
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
132
Package Type
PQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC68332ACEH20
Manufacturer:
MOTOROLA
Quantity:
1 000
Company:
Part Number:
MC68332ACEH20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
6.3.2.2 Transmit RAM
6.3.2.3 Command RAM
6.3.3 QSPI Pins
6-8
Data that is to be transmitted by the QSPI is stored in this segment. The CPU normally
writes one word of data into this segment for each queue command to be executed.
Information to be transmitted must be written to transmit RAM in a right-justified for-
mat. The QSPI cannot modify information in the transmit RAM. The QSPI copies the
information to its data serializer for transmission. Information remains in transmit RAM
until overwritten.
Command RAM is used by the QSPI in master mode. The CPU writes one byte of con-
trol information to this segment for each QSPI command to be executed. The QSPI
cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution by the QSPI pro-
ceeds from the address in NEWQP through the address in ENDQP (both of these
fields are in SPCR2).
The QSPI uses seven pins. These pins can be configured for general-purpose I/O
when not needed for QSPI application. When used for QSPI functions, the MOSI, MI-
SO, and SS pins should have pull-up resistors.
Table 6-2 shows QSPI input and output pins and their functions.
D00
D1E
RECEIVE
WORD
RAM
RRD
RR0
RR1
RR2
RRE
RRF
Freescale Semiconductor, Inc.
For More Information On This Product,
QUEUED SERIAL MODULE
Figure 6-3 QSPI RAM
Go to: www.freescale.com
D3E
D20
TRANSMIT
WORD
RAM
TRD
TR0
TR1
TR2
TRE
TRF
D40
D4F
COMMAND
BYTE
RAM
CRD
CR0
CR1
CR2
CRE
CRF
QSPI RAM MAP
USER’S MANUAL
MC68332