HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 36

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 3 Data Formats
3.5
The data format and valid data length varies with the instruction and DSP register. Instructions
that access the DSP data register fall into three categories: DSP data processing, X and Y data
transfer processing, and single data transfer processing.
3.5.1
When the A0 or A1 register is used as the source register in DSP fixed decimal point data
processing, the guard bits (32–39) are enabled. When any other register is used as the source
register (M0, M1, X0, X1, Y0, or Y1), the register data’s sign-extended portion goes to bits 32–39.
When the A0 or A1 register is used as the destination register, the guard bits (32–39) are enabled.
When any other register is used as the destination register, the resulting data’s bits 32–39 are
ignored.
DSP integer data processing is the same as DSP fixed decimal point data processing. The bottom
word (the bottom 16 bits, or bits 0–15) of the source register, however, is ignored. The bottom
word of the destination register is cleared with zeroes.
The top word (top 16 bits, or bits 16–31) of the source register for DSP logical data processing is
enabled. The bottom word and the guard bits of registers A0 and A1 are ignored. The top word of
the destination register is enabled. The bottom word and the guard bits of registers A0 and A1 are
cleared with zeroes.
3.5.2
The MOVX.W and MOVY.W instructions access the X and Y memory through the 16-bit X and
Y data buses. The part of data loaded to a register or stored from a register is the top word (bits
16–31). The bottom word is cleared with zeroes.
3.5.3
The MOVS.W and MOVS.L instructions can access any memory through the instruction data bus
(IDB). All DSP registers are connected to the IDB bus, which can serve as either the source and
destination register during a data transfer. There are two data transfer modes: word and longword.
In word mode, data is loaded to the top word of the DSP register or stored from the top word,
except for the A0G and A1G registers. In longword mode, data is loaded to the 32 bits of the DSP
register or stored from the 32 bits, except for the A0G and A1G registers.
Rev. 5.00 Jun 30, 2004 page 20 of 512
REJ09B0171-0500O
DSP Data Processing
X and Y Data Transfers
Single Data Transfers
DSP Instructions and Data Formats