HD64F7144F50V Renesas Electronics America, HD64F7144F50V Datasheet - Page 124

• Manufacturer Part Number: HD64F7144F50V
• Description: IC SUPERH MCU FLASH 256K 112QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7144r

Specifications of HD64F7144F50V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 74
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 112-QFP
• For Use With: HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)EDK7145 - DEV EVALUATION KIT SH7145
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Instruction Set
5.1.7
CPU Instructions That Support DSP Functions
Several system control instructions have been added to the CPU core instructions to support DSP
functions. The RS, RE, and MOD registers (which support modulo addressing) have been added,
and an RC counter has been added to the SR register. LDC and STC instructions have been added
to access these. LDS and STS instructions have also been added for accessing the DSP registers
DSR, A0, X0, X1, Y0, and Y1.
A SETRC instruction has been added for setting the value of the repeat counter (RC) in the SR
register (bits 16–27). When the operand of the SETRC instruction is immediate, 8 bits of
immediate data are set in bits 16–23 of the SR register and bits 24–27 are cleared. When the
operand is a register, the 12 bits 0–11 of the register are set in bits 16–27 of the SR register.
In addition to the new LDC instructions, the LDRE and LDRS instructions have been added for
setting the repeat start address and repeat end address in the RS and RE registers.
Table 5.9 shows the added instructions.
Rev. 5.00 Jun 30, 2004 page 108 of 512
REJ09B0171-0500O