MC56F8355VFGE Freescale Semiconductor, MC56F8355VFGE Datasheet
MC56F8355VFGE
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MC56F8355VFGE Summary of contents
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Data Sheet Preliminary Technical Data 56F8300 16-Bit Digital Signal Controllers MC56F8355 Rev. 17 08/2009 freescale.com ...
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... Digital Input Current Low and clarified Section 12.3. Table 10-1; also removed overall Table 13-1. Table 10-1). Deleted formula for Max Ambient Table 2-2. Clarified external reference Table 2-2. to 16KB. Table 2-2: Table 2- the design used through a 1K resistor. SS Freescale Semiconductor with 10-14. Preliminary ...
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... Remove the equation fragment from the bottom of • Table 10-23 Rev 17 footnote. Freescale Semiconductor Preliminary Description of Change — TDO pullup is not enabled — PWM pullup is not enabled — CAN_TX — remove pullup related text — Adding pullup is enabled to several rows for clarification — ...
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... R/W Control 6 * External A8-13 or GPIOA0-5 Address Bus Switch 5 GPIOB0-4 or A16-20 * External 4 D7-10 or GPIOF0-3 Data Bus Switch * Bus 6 GPIOD0-5 or CS2-7 Control * EMI not functional in this package; use as Clock GPIO pins PLL resets Clock XTAL R S Generator EXTAL C CLKO CLKMODE Freescale Semiconductor Preliminary ...
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... Stop and Wait Mode Disable Function . 121 6.9 Resets 122 Part 7 Security Features 122 7.1 Operation with Security Enabled . . . . . 122 7.2 Flash Access Blocking Mechanisms 123 Freescale Semiconductor Preliminary Table of Contents Part 8 General Purpose Input/Output (GPIO 125 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . 125 8.2 Memory Maps ...
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... Quadrature Decoder Temperature Sensor 1.1.3 Memory Note: Features in italics are NOT available in the 56F8155 device. 6 Table 1-1 Device Differences 56F8355 60MHz/60 MIPS 4KB 8KB 56F8355 Technical Data, Rev. 17 56F8155 40MHz/40MIPS Not Available Not Available Not Available Not Available Freescale Semiconductor Preliminary ...
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... In the 56F8355, two four-input Quadrature Decoders or two additional Quad Timers — In the 56F8155, one four-input Quadrature Decoder, which works in conjunction with Quad Timer A • Temperature Sensor can be connected, on the board, to any of the ADC inputs to monitor the on-chip temperature • Quad Timer: Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 56F8355/56F8155 Features 7 ...
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... The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. 8 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Data RAM. A total of 16KB of Boot Flash is incorporated for easy customer inclusion of field-programmable software routines that can be used to program the main Program Flash memory area. The Program Flash memory can be independently bulk erased or erased in pages; Program Flash page Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 ...
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... IP Bus Bridge. The figures do not show the 10 Figure 1-1 and Figure 56F8355 Technical Data, Rev. 17 1-2. Figure 1-1 illustrates how the Table 1-1 lists the Figure 1-2 Freescale Semiconductor Preliminary ...
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... C input channel as indicated. The timer can then be used to introduce a controllable delay before generating its output signal. The timer output then triggers the ADC. To fully understand this interaction, please see the 56F8300 Peripheral User Manual for clarification on the operation of all three of these peripherals. Freescale Semiconductor Preliminary Part 2, Signal/Connection Descriptions, 56F8355 Technical Data, Rev. 17 ...
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... The primary data RAM port is 32 bits wide. Other data ports are 12 pab[20:0] cdbw[31:0] xab1[23:0] xab2[23:0] Figure 1-1 System Bus Interfaces 56F8355 Technical Data, Rev. 17 Boot Flash Program Flash Program RAM EMI* 11 Address 4 Data 6 Control Data RAM Data Flash To Flash Control Logic IPBus Bridge Flash Memory Module IPBus 16 bits. Freescale Semiconductor Preliminary ...
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... Timer A 4 Quadrature Decoder 0 4 Timer D Timer B 4 Quadrature Decoder SCI 0 2 NOT available on the 56F8155 device. Freescale Semiconductor Preliminary To/From IPBus Bridge SPI 1 GPIO A GPIO B GPIO C GPIO D GPIO E GPIO F SPI 0 SCI 1 IPBus Figure 1-2 Peripheral Subsystem 56F8355 Technical Data, Rev. 17 ...
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... Data is written Secondary Data Memory Interface Peripheral Interface Bus are required for a complete description and proper design with the Freescale Literature Distribution Table 1-3 Chip Documentation Description 56F8355 Technical Data, Rev. 17 Centers, or online at Order Number DSP56800EERM MC56F8300UM MC56F83xxBLUM Freescale Semiconductor Preliminary ...
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... A high true (active high) signal is low or a low true (active low) signal is high. Examples: Signal/Symbol PIN PIN PIN PIN 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. Freescale Semiconductor Preliminary Table 1-3 Chip Documentation Description Logic State True False True False 56F8355 Technical Data, Rev ...
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... EMI not functional in these packages; use as GPIO pins. 16 Figure 2-1. In Table 2-2, each table row describes the signal or signals 4 ) pins serve as 2.5V V CAP DD_CORE 56F8355 Technical Data, Rev. 17 Number of Pins in Package 56F8355 56F8155 — — — — power inputs Freescale Semiconductor Preliminary ...
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... GPIO RXD0 (GPIOE1) TXD1 (GPIOD6) SCI1 or RXD1 (GPIOD7) GPIO JTAG/ EOnCE Port * not functional in this package; use as GPIO pins Figure 2-1 56F8355 Signals Identified by Functional Group 1. Alternate pin functionality is shown in parenthesis; pin direction/type shown is the default functionality. Freescale Semiconductor Preliminary V DD_IO ...
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... GPIOC0) (MOSI1, GPIOC1) SPI1 or GPIO (MISO1, GPIOC2) (SS1, GPIOC3) (GPIOC8 - 10) GPIO PWMB0 - 5 ISB0 - 2 (GPIOD10 - 12) PWMB FAULTB0 - 3 ANA0 - 7 ADCA V REF ANB0 - 7 ADCB TC0 - 1 (GPIOE8 - 9) Quad Timer C or GPIO (GPIOE10 - 13) IRQA Interrupt/ IRQB Program RESET Control RSTO 1 (128-pin LQFP) Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary State During Signal Description Reset I/O Power — This pin supplies 3.3V power to the chip I/O interface and also the Processor core throught the on-chip voltage regulator enabled. ADC Power — This pin supplies 3.3V power to the ADC modules. ...
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... The input clock can be selected to provide the clock directly to the core. This input clock can also be selected as the input clock for the on-chip PLL. 56F8355 Technical Data, Rev. 17 Signal Description (regulator enabled), SS (regulator disabled), DD and should be connected to a Freescale Semiconductor Preliminary ...
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... Output GPIOB1 28 (A17) GPIOB2 29 (A18) GPIOB3 30 (A19) Freescale Semiconductor Preliminary State During Signal Description Reset In reset, Clock Output — This pin outputs a buffered clock signal. Using output is the SIM CLKO Select Register (SIM_CLKOSR), this pin can be disabled programmed as any of the following: disabled, CLK_MSTR (system clock), IPBus clock, oscillator output, prescaler clock and postscaler clock ...
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... To deactivate the internal pullup resistor, clear the appropriate GPIO bit in the GPIOF_PUR register. Example: GPIOF0, clear bit 0 in the GPIOF_PUR register. Note: Primary function is not available in this package configuration; GPIO function must be used instead. 56F8355 Technical Data, Rev. 17 Part 6.5.7 for details. Freescale Semiconductor Preliminary ...
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... Input (GPIOE1) Input/ Output TXD1 40 Output (GPIOD6) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Port D GPIO — These six GPIO pins can be individually pullup programmed as input or output pins. enabled Chip Select — CS2 - CS7 may be programmed within the EMI module to act as chip selects for specific areas of the external memory map ...
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... Test Data Output — This tri-stateable output pin provides a serial output is output data stream from the JTAG/EOnCE port driven in the disabled shift-IR and shift-DR controller states, and changes on the falling edge of TCK. 56F8355 Technical Data, Rev. 17 Signal Description through a 2.2K resistor. DD Freescale Semiconductor Preliminary ...
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... Schmitt Input (TA1) Schmitt Input/ Output (GPIOC5) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Reset Input, Test Reset — input, a low signal on this pin provides a pulled high reset signal to the JTAG TAP controller. To ensure complete internally hardware reset, TRST should be asserted whenever RESET is asserted ...
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... Port E GPIO — This GPIO pin can be individually programmed as an input or output pin. After reset, the default state is SCLK0. To deactivate the internal pullup resistor, clear bit 4 in the GPIOE_PUR register. 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Output (GPIOE6) Input/ Output SS0 123 Input (GPIOE7) Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset In reset, SPI 0 Master Out/Slave In — This serial data pin is an output output is from a master device and an input to a slave device. The master disabled, ...
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... In the 56F8355, the default state after reset is PHASEB1. In the 56F8155, the default state is not one of the functions offered and must be reconfigured. To deactivate the internal pullup resistor, clear bit 1 in the GPIOC_PUR register. 56F8355 Technical Data, Rev. 17 Part Freescale Semiconductor Preliminary ...
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... Schmitt Input/ Output (SS1) Schmitt Input (GPIOC3) Schmitt Input/ Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, Index1 — Quadrature Decoder 1, INDEX input pullup enabled TB2 — Timer B, Channel 2 SPI 1 Master In/Slave Out — This serial data pin is an input to a master device and output from a slave device ...
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... PWMA outputs in cases where fault conditions originate off-chip. enabled To deactivate the internal pullup resistor, set the PWMA1 bit in the SIM_PUDR register. See In reset, PWMB0 - 5 — Six PWMB output pins. output is disabled 56F8355 Technical Data, Rev. 17 Part 6.5.6 for details. Part 6.5.6. Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... REFP Output V 91 REFMID V 90 REFN V 89 Input REFLO Freescale Semiconductor Preliminary State During Signal Description Reset Input, ISB0 - 2 — These three input current status pins are used for pullup top/bottom pulse width correction in complementary channel enabled operation for PWMB. Port D GPIO — These GPIO pins can be individually programmed as input or output pins ...
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... Port E GPIO — These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality. To deactivate the internal pullup resistor, clear the appropriate bit of the GPIOE_PUR register. See 56F8355 Technical Data, Rev. 17 Part 6.5.6 for details. Freescale Semiconductor Preliminary ...
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... Schmitt Input IRQB 53 RESET 78 Schmitt Input RSTO 77 Output Freescale Semiconductor Preliminary State During Signal Description Reset Input, TD0 - TD3 — Timer D, Channels and 3 pullup enabled Port E GPIO — These GPIO pins can be individually programmed as input or output pins. At reset, these pins default to Timer functionality. ...
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... Note: When this pin is tied low, the customer boot software should disable the internal pullup resistor by setting the EMI_MODE bit of the SIM_PUDR; see Part Note: This pin is internally tied low (to V 56F8355 Technical Data, Rev force the device 6.5. Freescale Semiconductor Preliminary ...
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... The internal oscillator is designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in in Figure 3-2. Follow the crystal supplier’s recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. Freescale Semiconductor Preliminary Prescaler CLK PLLDB PLL F ...
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... Peripheral User Manual. 36 EXTAL XTAL Sample External Crystal Parameters 750 Note: If the operating temperature range is limited to o below 85 CL2 3 Terminal Sample External Ceramic Resonator Parameters: EXTAL XTAL R = 750 56F8355 Technical Data, Rev (105 C junction), then Meg z Figure CLKMODE = 0 Freescale Semiconductor 3-3. Preliminary ...
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... Program RAM 4KB Data RAM 16KB Program Boot Flash 16KB Freescale Semiconductor Preliminary Set OCCS_COHL bit high when using an Note: When using an external clocking source EXTAL with this configuration, the input “CLKMODE” should be high and the COHL bit in the OSCTL V register should be set to 1 ...
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... Not valid; cannot boot externally if the Flash is secured and will actually configure to 00 state Mode 0 – Internal Boot; EMI is configured to use 16 address lines Mode 1 – External Boot; Flash Memory is not secured; EMI configuration is determined by the state of the EMI_MODE pin 56F8355 Technical Data, Rev Freescale Semiconductor Preliminary ...
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... Cannot be used since MA = EXTBOOT = 0 and the EMI is not available; information in shaded areas not applicable to 56F8355/56F8155. 2. This mode provides maximum compatibility with 56F80x parts while operating externally. 3. “EMI_MODE = 0”, EMI_MODE pin is tied to ground at boot up. 4. “EMI_MODE = 1”, EMI_MODE pin is tied to V Freescale Semiconductor Preliminary Chip Operating Mode Mode ...
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... Reserved for Reset Overlay Reserved for COP Reset Overlay P:$04 Illegal Instruction P:$06 SW Interrupt 3 P:$08 HW Stack Overflow P:$0A Misaligned Long Word Access P:$0C OnCE Step Counter P:$0E OnCE Breakpoint Unit 0 Reserved P:$12 OnCE Trace Buffer 56F8355 Technical Data, Rev. 17 Part Freescale Semiconductor Preliminary ...
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... SPI0 41 0-2 SCI1 42 0-2 SCI1 43 0-2 SCI1 45 0-2 SCI1 46 0-2 DEC1 47 0-2 Freescale Semiconductor Preliminary Vector Base Interrupt Function Address + P:$14 OnCE Transmit Register Empty P:$16 OnCE Receive Register Full Reserved P:$1C SW Interrupt 2 P:$1E SW Interrupt 1 P:$20 SW Interrupt 0 P:$22 IRQA ...
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... ADC B Conversion Compete / End of Scan P:$94 ADC A Conversion Complete / End of Scan P:$96 ADC B Zero Crossing or Limit Error P:$98 ADC A Zero Crossing or Limit Error P:$9A Reload PWM B P:$9C Reload PWM A P:$9E PWM B Fault P:$A0 PWM A Fault P:$A2 SW Interrupt LP 56F8355 Technical Data, Rev (Continued) Freescale Semiconductor Preliminary ...
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... Flash Memory content, their state is maintained during power-down and reset. During chip initialization, the content of these memory locations is loaded into Flash Memory control registers, detailed in the Flash Memory chapter of the 56F8300 Peripheral User Manual. These configuration parameters are located between $01_FFF7 and $01_FFFF. Freescale Semiconductor Preliminary Table 4-6 Data Memory Map 3 ...
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... Technical Data, Rev. 17 Data Memory FM_BASE + $14 Banked Registers Unbanked Registers FM_BASE + $00 8KB Note: Data Flash is NOT available in the 56F8155 device. Sector Size Page Size bits 512 x 16 bits 256 x 16 bits 256 x 16 bits bits 256 x 16 bits Register Name Freescale Semiconductor Preliminary ...
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... Data memory, except all peripheral registers should be read/written using word accesses only. Table 4-9 summarizes base addresses for the set of peripherals on the 56F8355 and 56F8155 devices. Freescale Semiconductor Preliminary Register Name External Signal Control Register ...
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... X:$00 F400 FC X:$00 F800 56F8355 Technical Data, Rev. 17 Table Number 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 4-27 4-28 4-29 4-30 4-31 4-32 4-33 4-34 4-35 4-36 4-37 4-38 Freescale Semiconductor Preliminary ...
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... Chip Select Timing Control Register 6 CSTC 7 $17 Chip Select Timing Control Register 7 BCR $18 Bus Control Register Table 4-11 Quad Timer A Registers Address Map Register Acronym TMRA0_CMP1 Freescale Semiconductor Preliminary (EMI_BASE = $00 F020) Register Description (TMRA_BASE = $00 F040) Address Offset Register Description $0 Compare Register 1 56F8355 Technical Data, Rev. 17 ...
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... Counter Register $16 Control Register $17 Status and Control Register $18 Comparator Load Register 1 $19 Comparator Load Register 2 $1A Comparator Status and Control Register Reserved $20 Compare Register 1 $21 Compare Register 2 $22 Capture Register $23 Load Register $24 Hold Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Table 4-12 Quad Timer B Registers Address Map Quad Timer B is NOT available in the 56F8155 device Register Acronym TMRB0_CMP1 TMRB0_CMP2 TMRB0_CAP TMRB0_LOAD TMRB0_HOLD TMRB0_CNTR TMRB0_CTRL TMRB0_SCR TMRB0_CMPLD1 Freescale Semiconductor Preliminary (TMRA_BASE = $00 F040) Address Offset Register Description $25 Counter Register $26 Control Register $27 Status and Control Register $28 ...
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... Counter Register $26 Control Register $27 Status and Control Register $28 Comparator Load Register 1 $29 Comparator Load Register 2 $2A Comparator Status and Control Register Reserved $30 Compare Register 1 $31 Compare Register 2 $32 Capture Register $33 Load Register $34 Hold Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... TMRC0_CNTR TMRC0_CTRL TMRC0_SCR TMRC0_CMPLD1 TMRC0_CMPLD2 TMRC0_COMSCR TMRC1_CMP1 TMRC1_CMP2 TMRC1_CAP TMRC1_LOAD TMRC1_HOLD TMRC1_CNTR TMRC1_CTRL TMRC1_SCR TMRC1_CMPLD1 TMRC1_CMPLD2 Freescale Semiconductor Preliminary (TMRB_BASE = $00 F080) Address Offset Register Description $35 Counter Register $36 Control Register $37 Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A ...
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... Status and Control Register $38 Comparator Load Register 1 $39 Comparator Load Register 2 $3A Comparator Status and Control Register (TMRD_BASE = $00 F100) Address Offset $0 Compare Register 1 $1 Compare Register 2 $2 Capture Register 56F8355 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...
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... TMRD1_LOAD TMRD1_HOLD TMRD1_CNTR TMRD1_CTRL TMRD1_SCR TMRD1_CMPLD1 TMRD1_CMPLD2 TMRD1_COMSCR TMRD2_CMP1 TMRD2_CMP2 TMRD2_CAP TMRD2_LOAD TMRD2_HOLD TMRD2_CNTR TMRD2_CTRL TMRD2_SCR TMRD2_CMPLD1 Freescale Semiconductor Preliminary (TMRD_BASE = $00 F100) Address Offset $3 Load Register $4 Hold Register $5 Counter Register $6 Control Register $7 Status and Control Register $8 Comparator Load Register 1 $9 Comparator Load Register 2 ...
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... Fault Control Register $2 Fault Status Acknowledge Register $3 Output Control Register $4 Counter Register $5 Counter Modulo Register $6 Value Register 0 $7 Value Register 1 $8 Value Register 2 $9 Value Register 3 $A Value Register 4 $B Value Register 5 56F8355 Technical Data, Rev. 17 Register Description Register Description Freescale Semiconductor Preliminary ...
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... PWMB_PMOUT PWMB_PMCNT PWMB_PWMCM PWMB_PWMVAL0 PWMB_PWMVAL1 PWMB_PWMVAL2 PWMB_PWMVAL3 PWMB_PWMVAL4 PWMB_PWMVAL5 PWMB_PMDEADTM PWMB_PMDISMAP1 PWMB_PMDISMAP2 PWMB_PMCFG PWMB_PMCCR PWMB_PMPORT PWMB_PMICCR Freescale Semiconductor Preliminary (PWMA_BASE = $00 F140) Address Offset Register Description $C Dead Time Register $D Disable Mapping Register 1 $E Disable Mapping Register 2 $F Configure Register $10 Channel Control Register $11 ...
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... Position Difference Counter Register $4 Position Difference Counter Hold Register $5 Revolution Counter Register $6 Revolution Hold Register $7 Upper Position Counter Register $8 Lower Position Counter Register $9 Upper Position Hold Register $A Lower Position Hold Register $B Upper Initialization Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... IPR 9 VBA FIM0 FIVAL0 FIVAH0 FIM1 FIVAL1 FIVAH1 IRQP 0 IRQP 1 IRQP 2 IRQP 3 IRQP 4 IRQP 5 ICTL Freescale Semiconductor Preliminary (DEC1_BASE = $00 F190) Address Offset Register Description $C Lower Initialization Register $D Input Monitor Register (ITCN_BASE = $00 F1A0) Address Offset Register Description $0 Interrupt Priority Register 0 $1 Interrupt Priority Register 1 ...
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... Low Limit Register 0 $12 Low Limit Register 1 $13 Low Limit Register 2 $14 Low Limit Register 3 $15 Low Limit Register 4 $16 Low Limit Register 5 $17 Low Limit Register 6 $18 Low Limit Register 7 $19 High Limit Register 0 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Table 4-21 Analog-to-Digital Converter Registers Address Map Register Acronym ADCB_CR 1 ADCB_CR 2 ADCB_ZCC ADCB_LST 1 ADCB_LST 2 ADCB_SDIS ADCB_STAT ADCB_LSTAT ADCB_ZCSTAT ADCB_RSLT 0 ADCB_RSLT 1 Freescale Semiconductor Preliminary (ADCA_BASE = $00 F200) Address Offset Register Description $1A High Limit Register 1 $1B High Limit Register 2 $1C High Limit Register 3 $1D High Limit Register 4 ...
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... High Limit Register 7 $21 Offset Register 0 $22 Offset Register 1 $23 Offset Register 2 $24 Offset Register 3 $25 Offset Register 4 $26 Offset Register 5 $27 Offset Register 6 $28 Offset Register 7 $29 Power Control Register ADC Calibration Register $2A 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Table 4-24 Serial Communication Interface 1 Registers Address Map Register Acronym SCI1_SCIBR SCI1_SCICR SCI1_SCISR SCI1_SCIDR Table 4-25 Serial Peripheral Interface 0 Registers Address Map Register Acronym SPI0_SPSCR SPI0_SPDSR SPI0_SPDRR SPI0_SPDTR Freescale Semiconductor Preliminary (TSENSOR_BASE = $00 F270) Address Offset Register Description $0 Control Register (SCI0_BASE = $00 F280) Address Offset Register Description $0 Baud Rate Register ...
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... Data Transmitter Register (COP_BASE = $00 F2C0) Address Offset Register Description $0 Control Register $1 Time Out Register $2 Counter Register (CLKGEN_BASE = $00 F2D0) Address Offset Register Description $0 Control Register $1 Divide-By Register $2 Status Register Reserved $4 Shutdown Register $5 Oscillator Control Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... GPIOA_RAWDATA Table 4-30 GPIOB Registers Address Map Register Acronym GPIOB_PUR GPIOB_DR GPIOB_DDR GPIOB_PER GPIOB_IAR GPIOB_IENR GPIOB_IPOLR GPIOB_IPR GPIOB_IESR GPIOB_PPMODE GPIOB_RAWDATA Freescale Semiconductor Preliminary (GPIOA_BASE = $00 F2E0) Address Offset Register Description $0 Pullup Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... Reset Value 0 x 1FFF 0 x 0000 0 x 0000 0 x 1FC0 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 0000 0 x 1FFF — Freescale Semiconductor Preliminary ...
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... GPIOE_RAWDATA Table 4-34 GPIOF Registers Address Map Register Acronym GPIOF_PUR GPIOF_DR GPIOF_DDR GPIOF_PER GPIOF_IAR GPIOF_IENR GPIOF_IPOLR GPIOF_IPR GPIOF_IESR GPIOF_PPMODE GPIOF_RAWDATA Freescale Semiconductor Preliminary (GPIOE_BASE = $00 F330) Register Description $0 Pullup Enable Register $1 Data Register $2 Data Direction Register $3 Peripheral Enable Register $4 Interrupt Assert Register ...
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... I/O Short Address Location Low Register (LVI_BASE = $00 F360) Address Offset $0 Control Register $1 Status Register (FM_BASE = $00 F400) Address Offset Register Description $0 Clock Divider Register $1 Module Control Register Reserved $3 Security High Half Register $4 Security Low Half Register 56F8355 Technical Data, Rev. 17 Register Description Freescale Semiconductor Preliminary ...
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... Table 4-38 FlexCAN Registers Address Map FlexCAN is NOT available in the 56F8155 device Register Acronym FCMCR FCCTL0 FCCTL1 FCTMR FCMAXMB FCRXGMASK_H FCRXGMASK_L FCRX14MASK_H FCRX14MASK_L FCRX15MASK_H Freescale Semiconductor Preliminary (FM_BASE = $00 F400) Address Offset Register Description Reserved Reserved $10 Protection Register (Banked) $11 Protection Boot Register (Banked) Reserved $13 ...
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... Message Buffer 1 Data Register $4E Message Buffer 1 Data Register Reserved $50 Message Buffer 2 Control / Status Register $51 Message Buffer 2 ID High Register $52 Message Buffer 2 ID Low Register $53 Message Buffer 2 Data Register $54 Message Buffer 2 Data Register $55 Message Buffer 2 Data Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... FCMB5_ID_HIGH FCMB5_ID_LOW FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB5_DATA FCMB6_CONTROL FCMB6_ID_HIGH FCMB6_ID_LOW FCMB6_DATA FCMB6_DATA FCMB6_DATA FCMB6_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $56 Message Buffer 2 Data Register Reserved $58 Message Buffer 3 Control / Status Register $59 Message Buffer 3 ID High Register $5A Message Buffer 3 ID Low Register ...
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... Message Buffer 9 Data Register $8E Message Buffer 9 Data Register Reserved $90 Message Buffer 10 Control / Status Register $91 Message Buffer 10 ID High Register $92 Message Buffer 10 ID Low Register $93 Message Buffer 10 Data Register $94 Message Buffer 10 Data Register $95 Message Buffer 10 Data Register 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... FCMB12_DATA FCMB13_CONTROL FCMB13_ID_HIGH FCMB13_ID_LOW FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB13_DATA FCMB14_CONTROL FCMB14_ID_HIGH FCMB14_ID_LOW FCMB14_DATA FCMB14_DATA Freescale Semiconductor Preliminary (FC_BASE = $00 F800) Address Offset Register Description $96 Message Buffer 10 Data Register Reserved $98 Message Buffer 11 Control / Status Register $99 Message Buffer 11 ID High Register $9A Message Buffer 11 ID Low Register ...
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... Message Buffer 14 Data Register Reserved $B8 Message Buffer 15 Control / Status Register $B9 Message Buffer 15 ID High Register $BA Message Buffer 15 ID Low Register $BB Message Buffer 15 Data Register $BC Message Buffer 15 Data Register $BD Message Buffer 15 Data Register $BE Message Buffer 15 Data Register Reserved 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... The following tables define the nesting requirements for each priority level. Table 5-1 Interrupt Mask Bit Definition 1 SR[ Core status register bits indicating current interrupt mask within the core. Table 5-2 Interrupt Priority Encoding IPIC_LEVEL[1:0] 00 Freescale Semiconductor Preliminary 4-5, Interrupt Vector Table Contents. 1 Permitted Exceptions SR[8] 0 Priorities Priorities Priorities 2, 3 ...
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... The core then fetches the instruction from the indicated vector adddress and not a JSR, the core starts its fast interrupt handling. 74 Current Interrupt 1 Priority Level Priority 0 Priorities Priority 1 Priorities 2, 3 Priorities Priority 3 Part 5.6.30.2 56F8355 Technical Data, Rev. 17 Required Nested Exception Priority Freescale Semiconductor Preliminary ...
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... A peripheral which requires a clock to generate interrupts will not be able to generate interrupts during Stop mode. The FlexCAN module can wake the device from Stop mode, and a reset will do just that, or IRQA and IRQB can wake it up. Freescale Semiconductor Preliminary any0 Level 0 82 -> ...
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... IRQ Pending Register 4 IRQ Pending Register 5 Interrupt Control Register 56F8355 Technical Data, Rev. 17 Section Location 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.6.10 5.6.11 5.6.12 5.6.13 5.6.14 5.6.15 5.6.16 5.6.17 5.6.18 5.6.19 5.6.20 5.6.21 5.6.22 5.6.23 5.6.30 Freescale Semiconductor Preliminary ...
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... FIM1 FIVAL1 $10 FIVAH1 $11 IRQP0 W R $12 IRQP1 W R $13 IRQP2 W Figure 5-2 ITCN Register Map Summary Freescale Semiconductor Preliminary Table 5-3 ITCN Register Summary Register Name STPCNT IPL FMERR IPL LOCK IPL GPIOE GPIOF FCMSGBUF IPL FCWKUP IPL IPL IPL SPI1_RCV IPL 0 ...
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... Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through PENDING [64:49] PENDING [80:65 VAB STPCNT IPL 56F8355 Technical Data, Rev PEND IRQB IRQA 1 IRQB STATE STATE INT_DIS EDG Freescale Semiconductor Preliminary 0 ING [81] IRQA EDG ...
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... EOnCE Transmit Register Empty Interrupt Priority Level (TX_REG IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through disabled by default. • IRQ disabled (default) • IRQ is priority level 1 • IRQ is priority level 2 Freescale Semiconductor Preliminary ...
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... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level FMERR IPL LOCK IPL LVI IPL 56F8355 Technical Data, Rev IRQB IPL IRQA IPL Freescale Semiconductor Preliminary 0 0 ...
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... External IRQ B Interrupt Priority Level (IRQB IPL)—Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through disabled by default. • IRQ disabled (default) • IRQ is priority level 0 Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Register Descriptions 81 ...
Page 82
... GPIOF Interrupt Priority Level (GPIOF IPL)—Bits 11–10 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default FCMSGBUF IPL FCWKUP IPL 56F8355 Technical Data, Rev FCERR IPL FCBOFF IPL Freescale Semiconductor Preliminary ...
Page 83
... FlexCAN Bus Off Interrupt Priority Level (FCBOFF IPL)— Bits 3–2 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Register Descriptions 83 ...
Page 84
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level SPI1_RCV IPL IPL 56F8355 Technical Data, Rev GPIOA IPL GPIOB IPL GPIOC IPL Freescale Semiconductor Preliminary ...
Page 85
... IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.6 Interrupt Priority Register 5 (IPR5) Base + $ Read DEC1_XIRQ DEC1_HIRQ IPL Write RESET Figure 5-8 Interrupt Priority Register 5 (IPR5) Freescale Semiconductor Preliminary SCI1_RCV SCI1_RERR IPL IPL IPL 56F8355 Technical Data, Rev. 17 ...
Page 86
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 86 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 87
... IRQ is priority level 1 • IRQ is priority level 2 5.6.7 Interrupt Priority Register 6 (IPR6) Base + $ Read TMRC0 IPL TMRD3 IPL Write RESET Figure 5-9 Interrupt Priority Register 6 (IPR6) Freescale Semiconductor Preliminary TMRD2 IPL TMRD1 IPL TMRD0 IPL 56F8355 Technical Data, Rev. 17 Register Descriptions ...
Page 88
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 88 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 89
... IRQ is priority level 1 • IRQ is priority level 2 5.6.8 Interrupt Priority Register 7 (IPR7) Base + $ Read TMRA0 IPL TMRB3 IPL Write RESET Figure 5-10 Interrupt Priority Register (IPR7) Freescale Semiconductor Preliminary TMRB2 IPL TMRB1 IPL TMRB0 IPL 56F8355 Technical Data, Rev. 17 Register Descriptions ...
Page 90
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 90 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 91
... IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 5.6.9 Interrupt Priority Register 8 (IPR8) Base + $ Read SCI0_RCV SCI0_RERR IPL Write RESET Figure 5-11 Interrupt Priority Register 8 (IPR8) Freescale Semiconductor Preliminary SCI0_TIDL SCI0_XMIT IPL IPL 56F8355 Technical Data, Rev. 17 Register Descriptions ...
Page 92
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 92 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 93
... Figure 5-12 Interrupt Priority Register 9 (IPR9) 5.6.10.1 PWM A Fault Interrupt Priority Level (PWMA_F IPL)—Bits 15–14 This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) Freescale Semiconductor Preliminary ...
Page 94
... This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 0 through 2. They are disabled by default. • IRQ disabled (default) • IRQ is priority level 0 • IRQ is priority level 1 • IRQ is priority level 2 94 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 95
... Vector Base Address Register (VBA) Base + $ Read Write RESET Figure 5-13 Vector Base Address Register (VBA) 5.6.11.1 Reserved—Bits 15–13 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. Freescale Semiconductor Preliminary VECTOR BASE ADDRESS 56F8355 Technical Data, Rev. 17 Register Descriptions 6 ...
Page 96
... The lower 16 bits of the vector address are used for Fast Interrupt 0. This register is combined with FIVAH0 to form the 21-bit vector address for Fast Interrupt 0 defined in the FIM0 register. 96 Part 5.3.1 for details FAST INTERRUPT 0 VECTOR ADDRESS LOW 56F8355 Technical Data, Rev FAST INTERRUPT Freescale Semiconductor Preliminary ...
Page 97
... Fast interrupts automatically become the highest-priority level 2 interrupt, regardless of their location in the interrupt table, prior to being declared as fast interrupt. Fast interrupt 0 has priority over Fast Interrupt 1. To determine the vector number of each IRQ, refer to Table 4-5. Freescale Semiconductor Preliminary ...
Page 98
... This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number FAST INTERRUPT 1 VECTOR ADDRESS LOW PENDING [16: 56F8355 Technical Data, Rev FAST INTERRUPT 1 VECTOR ADDRESS HIGH Freescale Semiconductor Preliminary ...
Page 99
... IRQ Pending (PENDING)—Bits 48–33 This register combines with the other five to represent the pending IRQs for interrupt vector numbers 2 through 81. • IRQ pending for this vector number • IRQ pending for this vector number Freescale Semiconductor Preliminary PENDING [32:17] ...
Page 100
... Write RESET Figure 5-25 IRQ Pending Register 5 (IRQP5) 5.6.23.1 Reserved—Bits 96–82 This bit field is reserved or not implemented. The bits are read as 1 and cannot be modified by writing. 100 PENDING [64:49 PENDING [80:65 56F8355 Technical Data, Rev PEND Freescale Semiconductor Preliminary ING [81] 1 ...
Page 101
... Nested interrupts may cause this field to be updated before the original interrupt service routine can read it. • Required nested exception priority levels are • Required nested exception priority levels are • Required nested exception priority levels are Freescale Semiconductor Preliminary VAB ...
Page 102
... Resets 5.7.1 Reset Handshake Timing The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset vector will be presented until the second rising clock edge after RESET is released. 102 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 103
... IRQs with fixed priorities: • Illegal Instruction • SW Interrupt 3 • HW Stack Overflow • Misaligned Long Word Access • SW Interrupt 2 • SW Interrupt 1 • SW Interrupt 0 • SW Interrupt LP These interrupts are enabled at their fixed priority levels. Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Resets 103 ...
Page 104
... Registers for software access to the JTAG ID of the chip 6.3 Operating Modes Since the SIM is responsible for distributing clocks and resets across the chip, it must understand the various chip operating modes and take appropriate action. These are: 104 56F8355 Technical Data, Rev clock cycles. Freescale Semiconductor Preliminary ...
Page 105
... The reset state for MB and MA will depend on the Flash secured state. See information on how the Operating Mode Register (OMR) MA and MB bits operate in this device. For additional information on the EX bit, see Manual. Note: The OMR is not a Memory Map register directly accessible in code through the acronym OMR. Freescale Semiconductor Preliminary ...
Page 106
... GPIO Peripheral Select Register Peripheral Clock Enable Register I/O Short Address Location High Register I/O Short Address Location Low Register 56F8355 Technical Data, Rev. 17 Section Location 6.5.1 6.5.2 6.5.3 6.5.3 6.5.3 6.5.3 6.5.4 6.5.5 6.5.6 6.5.7 6.5.8 6.5.9 6.5.10 6.5.10 Freescale Semiconductor Preliminary ...
Page 107
... R $5 SIM_SCR3 SIM_MSH_ $ SIM_LSH_ID SIM_PUDR PWMA1 W Reserved SIM_ $A CLKOSR SIM_GPS SIM_PCE EMI ADCB SIM_ISALH SIM_ISALL W = Reserved Figure 6-2 SIM Register Map Summary Freescale Semiconductor Preliminary FIELD FIELD FIELD FIELD EMI_ CAN RESET IRQ XBOOT PWMB PWMA0 MODE A23 A22 A21 ADCA ...
Page 108
... Bits in this register are set upon any system reset and are initialized only by a Power-On Reset (POR). A reset (other than POR) will only set bits in the register; bits are not cleared. Only software should clear this register. 108 56F8355 Technical Data, Rev ONCE SW STOP_ WAIT_ EBL RST DISABLE DISABLE Freescale Semiconductor Preliminary 0 0 ...
Page 109
... Reset. 6.5.2.6 Reserved—Bits 1–0 This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.3 SIM Software Control Registers (SIM_SCR0, SIM_SCR1, SIM_SCR2, and SIM_SCR3) Only SIM_SCR0 is shown below. SIM_SCR1, SIM_SCR2, and SIM_SCR3 are identical in functionality. Freescale Semiconductor Preliminary ...
Page 110
... GPIO function. Non-GPIO pins can have their pullups disabled by setting the appropriate bit in this register. Disabling pullups is done on a peripheral-by-peripheral basis (for pins not muxed with GPIO). Each bit in the register (see 110 FIELD Figure 6-8) corresponds to a functional group of pins. See 56F8355 Technical Data, Rev Freescale Semiconductor Preliminary ...
Page 111
... In this package, this input pin is double-bonded with the adjacent V changed order to reduce power consumption. 6.5.6.8 PWMB—Bit 8 This bit controls the pullup resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins. 6.5.6.9 PWMA0—Bit 7 This bit controls the pullup resistors on the FAULTA0, FAULTA1, and FAULTA2 pins. Freescale Semiconductor Preliminary ...
Page 112
... This bit field is reserved or not implemented read as 0 and cannot be modified by writing. 6.5.7.2 Alternate GPIOB Peripheral Function for A23 (A23)—Bit 9 • Peripheral output function of GPIOB7 is defined to be A23 112 A23 A22 A21 56F8355 Technical Data, Rev. 17 Figure 6- CLK A20 CLKOSEL DIS Freescale Semiconductor Preliminary 0 0 ...
Page 113
... Reserved for factory test—SYS_CLK2 (from OCCS) • 01110 = Reserved for factory test—SYS_CLK_DIV2 • 01111 = Reserved for factory test—SYS_CLK_D • 10000 = ADCA clock • 10001 = ADCB clock Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Register Descriptions 113 ...
Page 114
... See the “Switch Matrix for Inputs to the Timer” table in the 56F8300 Peripheral User Manual for the definition of timer inputs based on the — Quad Decoder mode configuration. 56F8355 Technical Data, Rev. 17 I/O Pad Control 1 Comments Freescale Semiconductor Preliminary ...
Page 115
... GPIOC2 (C2)—Bit 2 This bit selects the alternate function for GPIOC2. • INDEX1/TB2 (default) • MISO1 6.5.8.4 GPIOC1 (C1)—Bit 1 This bit selects the alternate function for GPIOC1. • PHASEB1/TB1 (default) • MOSI1 Freescale Semiconductor Preliminary Control Registers — 1 — — 1 — ...
Page 116
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.5 Decoder 1 Enable (DEC1)—Bit 11 Each bit controls clocks to the indicated peripheral. • Clocks are enabled 116 TMRB TMRA SCI 1 SCI 56F8355 Technical Data, Rev SPI 1 SPI 0 PWMB Freescale Semiconductor 0 PWMA 1 Preliminary ...
Page 117
... The clock is not provided to the peripheral (the peripheral is disabled) 6.5.9.12 Serial Communications Interface 0 Enable (SCI0)—Bit 4 Each bit controls clocks to the indicated peripheral. • Clocks are enabled • The clock is not provided to the peripheral (the peripheral is disabled) Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Register Descriptions 117 ...
Page 118
... If this register is set to something other than the top of memory (EOnCE register space) and the EX bit in the OMR is set to 1, the JTAG port cannot access the on-chip EOnCE registers, and debug functions will be affected. 118 56F8355 Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
Page 119
... Figure 6-14 I/O Short Address Location High Register (SIM_ISALH) 6.5.10.1 Input/Output Short Address Low (ISAL[23:22])—Bit 1–0 This field represents the upper two address bits of the “hard coded” I/O short address. Freescale Semiconductor Preliminary “ Hard Coded” Address Portion ...
Page 120
... Peripherals are active and can produce interrupts if they have not been masked off. Interrupts will cause the core to come out of its suspended state and resume normal operation. Typically used for power-conscious applications. 56F8355 Technical Data, Rev (OCCS), and the 56F8300 . Table 6-3 Description Freescale Semiconductor Preliminary 0 1 ...
Page 121
... SYS_CLK = 60MHz. 6.8 Stop and Wait Mode Disable Function Permanent Disable Reprogrammable Disable Clock Select Freescale Semiconductor Preliminary Peripheral Clocks The only possible recoveries from Stop mode are: 1. CAN traffic (1st message will be lost) 2. Non-clocked interrupts 3. COP reset 4. External reset 5. Power-on reset ...
Page 122
... Only two bytes within this field are used to enable or disable security. Refer to the Flash Memory section in the 56F8300 Peripheral User Manual for the state of the security bytes and the resulting state 122 56F8355 Technical Data, Rev. 17 Part 6.5.1. This procedure 21 clock cycles to permit Freescale Semiconductor Preliminary ...
Page 123
... FM erase algorithm. This register must be set with appropriate values before the lockout sequence can begin. Refer to the JTAG section of the 56F8300 Peripheral User Manual for more details on setting this register value. Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 ...
Page 124
... FM_CLKDIV[6:0] value of $13 or $14, respectively. 150[kHz] EXAMPLE 2: In this example, the system clock has been set up with a value of 32MHz, making the FM 124 Figure 7-1. FM_CLKDIV[6] will map to the Flash Memory input clock 7 FMCLKD SYS_CLK (2) 200[kHz] < < (DIV + 1) 56F8355 Technical Data, Rev. 17 DIVIDER 7 Freescale Semiconductor Preliminary ...
Page 125
... FM configuration field last. Part 8 General Purpose Input/Output (GPIO) 8.1 Introduction This section is intended to supplement the GPIO information found in the 56F8300 Peripheral User Manual and contains only chip-specific information. This information supercedes the generic information Freescale Semiconductor Preliminary ( ) SYS_CLK ...
Page 126
... EMI Address pins - Not available in this package 4 pins - DEC1 / TMRB / SPI1 4 pins - DEC0 / TMRA 3 pins - PWMA current sense 56F8355 Technical Data, Rev. 17 through 4-34 define the actual reset Reset Function EMI Address N/A GPIO N/A DEC1 / TMRB DEC0 / TMRA PWMA current sense Freescale Semiconductor Preliminary ...
Page 127
... Freescale Semiconductor Preliminary Peripheral Function 2 pins - EMI CSn 4 pins - EMI CSn - Can only be used as GPIO 2 pins - SCI1 2 pins - EMI CSn - Not available in this package 3 pins - PWMB current sense 2 pins - SCI0 2 pins - EMI Address pins - Not available in this package 4 pins - SPI0 2 pins - TMRC ...
Page 128
... N/A 10 N/A 11 N/A 12 N/A 13 N/A 0 GPIO 1 GPIO 2 GPIO 3 GPIO 4 GPIO 5 N/A 6 N/A 7 N/A 56F8355 Technical Data, Rev. 17 Functional Signal Package Pin # A10 1 18 A11 1 19 A12 1 20 A13 1 27 A16 1 28 A17 1 29 A18 1 30 A19 A20 / Prescaler_clock 31 Freescale Semiconductor Preliminary ...
Page 129
... Table 8-3 GPIO External Signals Map (Continued) Pins in shaded rows are not available in 56F8355 / 56F8155 Pins in italics are NOT available in the 56F8155 device GPIO Port GPIO Bit GPIOC GPIOD Freescale Semiconductor Preliminary Reset Function 0 Peripheral 1 Peripheral 2 Peripheral 3 Peripheral 4 Peripheral 5 Peripheral 6 Peripheral ...
Page 130
... N/A 10 N/A 11 N/A 12 N/A 13 N/A 14 N/A 15 N/A 56F8355 Technical Data, Rev. 17 Functional Signal Package Pin # TXD0 7 RXD0 8 SCLK0 124 MOSI0 126 MISO0 125 SS0 123 TC0 111 TC1 113 TD0 107 TD1 108 TD2 109 TD3 110 D10 Freescale Semiconductor Preliminary ...
Page 131
... Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Note: The 56F8155 device is specified to meet Industrial requirements only; CAN is NOT available on the 56F8155 device. Freescale Semiconductor Preliminary marketing representative are stress ratings only, and functional operation at the maximum ...
Page 132
... OUT V Pin Group STG T STG 56F8355 Technical Data, Rev. 17 Min Max Unit - 0.3 4 0.3 4 0.3 4 0.3 3.0 V -0.3 6.0 V -0.3 4.0 V -0.3 4 6.0 -0.3 6.0 V -40 125 °C -40 105 °C -40 150 °C -40 125 °C -55 150 °C -55 150 °C Freescale Semiconductor Preliminary ...
Page 133
... Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 6. See Part 12.1 for more details on thermal design considerations Junction temperature Freescale Semiconductor Preliminary Min 2000 200 500 ...
Page 134
... DDA 2 — V +0.3 DDA -0.3 — .8 — — -4 — — -8 — — -12 — — 4 — — 8 — — 12 -40 — 125 -40 — 105 10,000 — — 10,000 — — 15 — — Freescale Semiconductor Preliminary Unit MHz °C °C Cycles Cycles Years ...
Page 135
... Schmitt Trigger Input V HYS Hysteresis Input Capacitance C (EXTAL/XTAL) Output Capacitance C OUTC (EXTAL/XTAL) Input Capacitance C Output Capacitance C OUT See Pin Groups in Table 10-1. Freescale Semiconductor Preliminary Notes Min 2.4 OH — OL Pin Groups — IH Pin Group — Pin Group 13 Pin Group 12 — Pin Groups ...
Page 136
... ADC powered on and clocked • 60MHz Device Clock 70uA 2.5mA • All peripheral clocks are enabled • ADC powered off 56F8355 Technical Data, Rev Volts Typ Max Units 1.8 1.9 V 2.14 — V 2.7 — V 110 130 A Test Conditions Freescale Semiconductor Preliminary ...
Page 137
... I Mode DD_Core RUN1_MAC 150 mA Wait3 86mA Stop1 900 A Stop2 100 Output Switching Freescale Semiconductor Preliminary I I DD_ADC DD_OSC_PLL • 8MHz Device Clock 0uA 155uA • All peripheral clocks are off • ADC powered off • PLL powered off • External Clock is off ...
Page 138
... Min m — 56F8355 Technical Data, Rev. 17 Typical Max Unit — 2.75 V — 2.75 V — 2.75 V — 700 mA 5 — 30 minutes Typical Max Unit 0 0. — 200 ps — 175 ps 1 100 150 Typical Max Unit 7.762 — mV/°C Freescale Semiconductor A A Preliminary ...
Page 139
... Figure 10-2 Input Signal Measurement References Figure 10-3 shows the definitions of the following signal states: • Active state, when a bus or signal is driven, and enters a low impedance state • Tri-stated, when a bus or signal is placed in a high impedance state Freescale Semiconductor Preliminary Symbol Min ...
Page 140
... Symbol Min osc t 3 — rise t — fall 56F8355 Technical Data, Rev. 17 and V OH Data3 Valid Data3 Data Active Typ Max Unit — — s — — ms — — Typ Max Unit — 120 MHz — — ns — — Freescale Semiconductor Preliminary ...
Page 141
... Table 10-15 Crystal Oscillator Parameters Characteristic Crystal Start-up time Resonator Start-up time Crystal ESR Crystal Peak-to-Peak Jitter Crystal Min-Max Period Variation Resonator Peak-to-Peak Jitter Resonator Min-Max Period Variation Freescale Semiconductor Preliminary t PW – Figure 10-4 External Clock Timing Table 10-14 PLL Timing ...
Page 142
... Min t 16T RA t 1.5T IRW t 18T FAST 14T 56F8355 Technical Data, Rev. 17 Typ Max Unit 250 290 A 80 110 1,2 Typical Unit See Figure Max — ns 10-5 — ns 10-6 — ns 10-7 — — ns 10-9 t RDA First Fetch Freescale Semiconductor Preliminary ...
Page 143
... A0–A15 Figure 10-8 Interrupt from Wait State Timing t IW IRQA A0–A15 Figure 10-9 Recovery from Stop State Using Asynchronous Interrupt Timing Freescale Semiconductor Preliminary Reset, Stop, Wait, Mode Select, and Interrupt Timing t IRW First Interrupt Instruction Execution a) First Interrupt Instruction Execution ...
Page 144
... Freescale Semiconductor Preliminary ...
Page 145
... SS (Input) SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) MISO (Input) MOSI (Output) Figure 10-10 SPI Master Timing (CPHA = 0) Freescale Semiconductor Preliminary SS is held High on master MSB in Bits 14– Master MSB out Bits 14– 56F8355 Technical Data, Rev. 17 Serial Peripheral Interface (SPI) Timing ...
Page 146
... Figure 10-12 SPI Slave Timing (CPHA = 0) 146 SS is held High on master MSB in Bits 14– Master MSB out Bits 14– ELD Slave MSB out Bits 14– MSB in Bits 14–1 56F8355 Technical Data, Rev LSB in (ref Master LSB out ELG Slave LSB out LSB in Freescale Semiconductor Preliminary ...
Page 147
... Figure 10-13 SPI Slave Timing (CPHA = 1) 10.10 Quad Timer Timing Characteristic Timer input period Timer input high / low period Timer output period Timer output high / low period 1. In the formulas listed the clock cycle. For 60MHz operation 16.67ns. 2. Parameters listed are guaranteed by design. Freescale Semiconductor Preliminary ...
Page 148
... Parameters listed are guaranteed by design. Phase A (Input) Phase B (Input) Figure 10-15 Quadrature Decoder Timing 148 P INHL OUTHL OUT Figure 10-14 Timer Timing Symbol Min 56F8355 Technical Data, Rev INHL P OUTHL 1, 2 Max Unit See Figure — ns 10-15 — ns 10-15 — ns 10- Freescale Semiconductor Preliminary ...
Page 149
... TXD SCI receive data pin (Input) 10.13 Controller Area Network (CAN) Timing Note: CAN is NOT available in the 56F8155 device. Characteristic Baud Rate Bus Wake Up detection 1. Parameters listed are guaranteed by design Freescale Semiconductor Preliminary Table 10-20 SCI Timing Min BR — 0.965/BR PW 0.965/BR PW ...
Page 150
... Figure 10-19 Test Clock Input Timing Diagram 150 T WAKEUP Table 10-22 JTAG Timing Symbol Min f DC SYS_CLK SYS_CLK — — TRST 1 )/2 56F8355 Technical Data, Rev. 17 Max Unit See Figure MHz 10-19 MHz 10-19 — ns 10-19 — ns 10-20 — ns 10- 10- 10-20 — ns 10- Freescale Semiconductor Preliminary ...
Page 151
... Analog-to-Digital Converter (ADC) Parameters Characteristic Input voltages Resolution 1 Integral Non-Linearity Differential Non-Linearity Monotonicity ADC internal clock Conversion range ADC channel power-up time ADC reference circuit power-up time Freescale Semiconductor Preliminary t DS Input Data Valid TRST Figure 10-21 TRST Timing Diagram ...
Page 152
... AIC 5 — — — 1 — — +/- .004 +/- .015 +/- 15 +/- 35 mV Figure 10-22 — LSBs TBD 0.010380 TBD -31.7 -60 — — REFLO 64.6 — 59.1 — 60.6 — 61.1 — 9.6 — Bits 3 LSB — Freescale Semiconductor Preliminary — — — ...
Page 153
... Although not guaranteed believed that calibration will produce results similar to those shown above for any population of parts, including those which represent processing and temperature extremes. Freescale Semiconductor Preliminary = 0.60V and 2.70V in 56F8355 Technical Data, Rev ...
Page 154
... A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage current, 154 - while the other charges to the analog input voltage. When REFH REFH REFLO 2 S2 56F8355 Technical Data, Rev The switches switch REFH REFH C1 S 1pF Freescale Semiconductor Preliminary ...
Page 155
... For instance, if there is a total of eight PWM outputs driving 10mA into LEDs, then P = 8*.5*.01 = 40mW. In previous discussions, power consumption due to parasitics associated with pure input pins is ignored assumed to be negligible. Freescale Semiconductor Preliminary 2 *F CMOS power dissipation corresponding to the Intercept 1 ...
Page 156
... ANB5 ANB4 ANB3 ANB2 ANB1 ANB0 V SSA_ADC V DDA_ADC V REFH V REFP V REFMID V REFN V REFLO TEMP_SENSE ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 CLKMODE RESET RSTO V DD_IO V 3 CAP EXTAL XTAL V DDA_OSC_PLL OCR_DIS FAULTA3 FAULTA2 FAULTA1 FAULTA0 65 PWMA5 V SS Freescale Semiconductor Preliminary ...
Page 157
... GPIOA2 18 1 GPIOA3 19 1 GPIOA4 20 1 GPIOA5 220 1 GPIOF0 23 1 GPIOF1 24 1 GPIOF2 25 V DD_IO 26 1 GPIOF3 27 GPIOB0 28 GPIOB1 Freescale Semiconductor Preliminary Signal Name Pin No. 33 PWMB1 65 34 PWMB2 DD_IO 37 PWMB3 69 38 PWMB4 70 39 PWMB5 71 40 TXD1 72 41 RXD1 73 42 ...
Page 158
... PWMA4 96 Figure 11-1 shows the package outline for the 128-pin LQFP case, 56F8355 Technical Data, Rev. 17 Signal Name Pin No. Signal Name V 125 MISO0 REFH V 126 MOSI0 DDA_ADC V 127 PHASEA0 SSA_ADC ANB0 128 PHASEB0 Table 11-1 lists the pin-out Freescale Semiconductor Preliminary ...
Page 159
... PWMB3 PWMB4 39 Figure 11-2 Top View, 56F8155 128-Pin LQFP Package Table 11-2 56F8155 128-Pin LQFP Package Identification by Pin Number Pin No. Signal Name Pin No. 1 INDEX0 2 HOME0 Freescale Semiconductor Preliminary Orientation Mark Signal Name Pin No. 33 PWMB1 65 34 PWMB2 66 56F8355 Technical Data, Rev. 17 ...
Page 160
... TRST ANA3 115 TCK ANA4 116 TMS AN5 117 TDI ANA6 118 TDO ANA7 119 120 NC V 121 NC REFLO V 122 V REFN CAP V 123 SS0 REFMID V 124 SCLK0 REFP V 125 MISO0 REFH V 126 MOSI0 DDA_ADC V 127 PHASEA0 SSA_ADC Freescale Semiconductor 1 2 Preliminary ...
Page 161
... Table 11-2 56F8155 128-Pin LQFP Package Identification by Pin Number (Continued) Pin No. Signal Name Pin No. 32 PWMB0 1. Primary function is not available in this package configuration; GPIO function must be used instead. Freescale Semiconductor Preliminary Signal Name Pin No 56F8355 Technical Data, Rev. 17 56F8155 Package and Pin-Out Information Signal Name Pin No ...
Page 162
... Technical Data, Rev. 17 MILLIMETERS DIM MIN MAX A --- 1.60 A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 22.00 BSC D1 20.00BSC e 0.50 BSC E 16.00 BSC E1 14.00 BSC L 0.45 0.75 L1 1.00 REF L2 0.50 REF S 0.20 --- R1 0.08 --- R2 0.08 0. --- Freescale Semiconductor Preliminary ...
Page 163
... where Thermocouple temperature on top of package ( T Freescale Semiconductor Preliminary , can be obtained from the equation C/W) . For instance, the user can change the size of the heat CA ) can be used to determine the junction temperature with 56F8355 Technical Data, Rev ...
Page 164
... Use at least a four-layer Printed Circuit Board (PCB) with two inner layers for V 164 o C)/W CAUTION of any voltages (GND) pin /V Ceramic and tantalum capacitors tend to provide better DDA SSA. 56F8355 Technical Data, Rev. 17 higher than pin on the device, and from the DD and V (GND and Freescale Semiconductor Preliminary ...
Page 165
... Flash, RAM and internal logic are powered from the core regulator output • and V 2 are not connected in the customer system PP PP • All circuitry, analog and digital, shares a common V V DDA_OSC_PLL REG OSC Freescale Semiconductor Preliminary layers of the PCB with approximately 100 F, preferably with a high-grade , V REF DDA pins. bus CAP ...
Page 166
... Technical Data, Rev. 17 Ambient Temperature Order Number Range 60 -40° 105°C MC56F8355VFG60 60 -40° 125°C MC56F8355MFG60 40 -40° 105°C MC56F8155VFG 60 -40° 105°C MC56F8355VFGE* 60 -40° 125°C MC56F8355MFGE* 40 -40° 105°C MC56F8155VFGE* Freescale Semiconductor Preliminary ...
Page 167
... Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Power Distribution and I/O Ring Implementation 167 ...
Page 168
... Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Power Distribution and I/O Ring Implementation 169 ...
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... Technical Data, Rev. 17 Freescale Semiconductor Preliminary ...
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... THIS PAGE IS INTENTIONALLY BLANK Freescale Semiconductor Preliminary 56F8355 Technical Data, Rev. 17 Power Distribution and I/O Ring Implementation 171 ...
Page 172
... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended ...