MCF53012CQT240 Freescale Semiconductor, MCF53012CQT240 Datasheet - Page 34
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MCF53012CQT240
Manufacturer Part Number
MCF53012CQT240
Description
MCU 32BIT COLDFIRE EMAC 208LQFP
Manufacturer
Freescale Semiconductor
Series
MCF5301xr
Datasheet
1.MCF53010CQT240.pdf
(62 pages)
Specifications of MCF53012CQT240
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
240MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, PWM, WDT
Number Of I /o
61
Program Memory Size
16KB (16K x 8)
Program Memory Type
Cache
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-LQFP
Processor Series
MCF5301x
Core
ColdFire V3
Data Bus Width
32 bit
Data Ram Size
128 KB
Interface Type
UART, I2C, SPI, SSI, Ethernet
Maximum Clock Frequency
20 MHz to 400 MHz
Number Of Programmable I/os
61
Number Of Timers
8
Operating Supply Voltage
3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JLINK-CF-BDM26, EWCF
Development Tools By Supplier
M53015EVB, M53017KIT, M53017MOD
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Preliminary Electrical Characteristics
5.10
The MCF53017 device is compliant with industry standard USB 2.0 specification.
5.11
This section provides the AC timings for the SSI in master (clocks driven) and slave modes (clocks input). All timings are given
for non-inverted serial clock polarity (SSI_TCR[TSCKP] = 0, SSI_RCR[RSCKP] = 0) and a non-inverted frame sync
(SSI_TCR[TFSI] = 0, SSI_RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timings
remain valid by inverting the clock signal (SSI_BCLK) and/or the frame sync (SSI_FS) shown in the figures below.
34
1
2
3
1
Num
Num
S10
All timings specified with a capactive load of 25pF.
SSI_MCLK can be generated from SSI_CLKIN or a divided version of the internal system clock (SYSCLK).
SSI_BCLK can be derived from SSI_CLKIN or a divided version of SYSCLK. If the SYSCLK is used, the minimum
divider is 6. If the SSI_CLKIN input is used, the programmable dividers must be set to ensure that SSI_BCLK does
not exceed 4 x f
S11
S12
S13
S14
S15
S16
S17
S18
All timings specified with a capactive load of 25pF.
S1
S2
S3
S4
S5
S6
S7
S8
S9
USB On-The-Go
SSI Timing Specifications
SSI_MCLK cycle time
SSI_MCLK pulse width high / low
SSI_BCLK cycle time
SSI_BCLK pulse width
SSI_BCLK to SSI_FS output valid
SSI_BCLK to SSI_FS output invalid
SSI_BCLK to SSI_TXD valid
SSI_BCLK to SSI_TXD invalid / high impedence
SSI_RXD / SSI_FS input setup before SSI_BCLK
SSI_RXD / SSI_FS input hold after SSI_BCLK
SSI_BCLK cycle time
SSI_BCLK pulse width high / low
SSI_FS input setup before SSI_BCLK
SSI_FS input hold after SSI_BCLK
SSI_BCLK to SSI_TXD / SSI_FS output valid
SSI_BCLK to SSI_TXD / SSI_FS output invalid / high
impedence
SSI_RXD setup before SSI_BCLK
SSI_RXD hold after SSI_BCLK
SYS
.
Description
Description
Preliminary—Subject to Change Without Notice
Table 17. SSI Timing - Master Modes
Table 18. SSI Timing — Slave Modes
MCF5301x Data Sheet, Rev. 5
Symbol
Symbol
t
t
t
MCLK
BCLK
BCLK
8 × t
8 × t
8 × t
45%
45%
45%
Min
Min
1
1
–2
10
10
10
—
—
—
0
0
2
0
2
SYS
SYS
SYS
55%
55%
55%
Max
Max
15
15
15
—
—
—
—
—
—
—
—
—
—
—
—
Freescale Semiconductor
Units
t
Units
t
t
MCLK
BCLK
BCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Notes
2
3