C8051F121-GQ Silicon Laboratories Inc, C8051F121-GQ Datasheet - Page 238
C8051F121-GQ
Manufacturer Part Number
C8051F121-GQ
Description
IC 8051 MCU FLASH 128K 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F12xr
Specifications of C8051F121-GQ
Program Memory Type
FLASH
Program Memory Size
128KB (128K x 8)
Package / Case
64-TQFP, 64-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
100MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
32
Ram Size
8.25K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F1x
Core
8051
Data Bus Width
8 bit
Data Ram Size
8.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
100 MHz
Number Of Programmable I/os
32
Number Of Timers
5
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F120DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 12-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
32
Ram Memory Size
8448Byte
Cpu Speed
100MHz
No. Of Timers
5
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1225
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F121-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Company:
Part Number:
C8051F121-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
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18.1. Ports 0 through 3 and the Priority Crossbar Decoder
The Priority Crossbar Decoder, or “Crossbar”, allocates and assigns Port pins on Port 0 through Port 3 to
the digital peripherals (UARTs, SMBus, PCA, Timers, etc.) on the device using a priority order. The Port
pins are allocated in order starting with P0.0 and continue through P3.7 if necessary. The digital peripher-
als are assigned Port pins in a priority order which is listed in Figure 18.3, with UART0 having the highest
priority and CNVSTR2 having the lowest priority.
18.1.1. Crossbar Pin Assignment and Allocation
The Crossbar assigns Port pins to a peripheral if the corresponding enable bits of the peripheral are set to
a logic 1 in the Crossbar configuration registers XBR0, XBR1, and XBR2, shown in SFR Definition 18.1,
SFR Definition 18.2, and SFR Definition 18.3. For example, if the UART0EN bit (XBR0.2) is set to a
logic 1, the TX0 and RX0 pins will be mapped to P0.0 and P0.1 respectively.
Because UART0 has the highest priority, its pins will always be mapped to P0.0 and P0.1 when UART0EN
is set to a logic 1. If a digital peripheral’s enable bits are not set to a logic 1, then its ports are not accessi-
ble at the Port pins of the device. Also note that the Crossbar assigns pins to all associated functions when
a serial communication peripheral is selected (i.e. SMBus, SPI, UART). It would be impossible, for exam-
238
TX0
RX0
SCK
MISO
MOSI
NSS
SDA
SCL
TX1
RX1
CEX0
CEX1
CEX2
CEX3
CEX4
CEX5
ECI
CP0
CP1
T0
/INT0
T1
/INT1
T2
T2EX
T4
T4EX
/SYSCLK
CNVSTR0
CNVSTR2
PIN I/O 0
Figure 18.3. Priority Crossbar Decode Table (EMIFLE = 0; P1MDIN = 0xFF)
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1
●
●
● ● ● ● ●
● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ●
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2
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●
● ● ● ● ●
● ● ● ● ● ● ●
● ● ● ● ● ● ● ● ●
●
3
P0
●
● ● ● ● ● ● ● ● ●
●
4
●
● ● ● ● ● ● ● ● ●
●
5
● ● ● ● ● ● ● ● ●
6
NSS is not assigned to a port pin when the SPI is placed in 3-wire mode
● ● ● ● ● ● ● ● ●
7
0
AIN2 Inputs/Non-muxed Addr H
1
2
3
P1
4
5
6
7
Muxed Addr H/Non-muxed Addr L
0
Rev. 1.4
1
2
3
P2
4
5
6
7
0
Muxed Data/Non-muxed Data
1
2
3
P3
4
5
6
7
Crossbar Register Bits
UART0EN:
UART1EN:
CNVSTE0: XBR2.0
CNVSTE2: XBR2.5
SMB0EN:
PCA0ME:
SYSCKE: XBR1.7
SPI0EN:
T2EXE: XBR1.6
T4EXE: XBR2.4
ECI0E: XBR0.6
INT0E: XBR1.2
INT1E: XBR1.4
CP0E: XBR0.7
CP1E: XBR1.0
T0E: XBR1.1
T1E: XBR1.3
T2E: XBR1.5
T4E: XBR2.3
XBR0.2
XBR0.1
XBR0.0
XBR2.2
XBR0.[5:3]
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