C8051F121-GQ Silicon Laboratories Inc, C8051F121-GQ Datasheet - Page 195

• Manufacturer Part Number: C8051F121-GQ
• Description: IC 8051 MCU FLASH 128K 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F121-GQ

• Program Memory Type: FLASH
• Program Memory Size: 128KB (128K x 8)
• Package / Case: 64-TQFP, 64-VQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 100MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 32
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F1x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 8.25 KB
• Interface Type: I2C/SMBus/SPI/UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F120DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 8-bit or 8-ch x 12-bit
• On-chip Dac: 2-ch x 12-bit
• No. Of I/o's: 32
• Ram Memory Size: 8448Byte
• Cpu Speed: 100MHz
• No. Of Timers: 5
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1224 - DEVKIT-F120/21/22/23/24/25/26/27
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1225

–40 to +85 °C unless otherwise specified
*Note: The maximum operating frequency of the C8051F124/5/6/7 is 50 MHz
Bits 7–6: UNUSED: Read = 00b; Write = don’t care.
Bits 5–4: PLLICO1-0: PLL Current-Controlled Oscillator Control Bits.
Bits 3–0: PLLLP3-0: PLL Loop Filter Control Bits.
R/W
Bit7
(Divided Reference Frequency)
-
PLL Output Frequency
Selection is based on the desired output frequency, according to the following table:
Selection is based on the divided PLL reference clock, according to the following table:
Input Frequency
Divided PLL Reference Clock
Parameter
R/W
Bit6
-
PLL Output Clock
12.2–19.5 MHz
7.8–12.5 MHz
65–100 MHz
PLLICO1 PLLICO0
Table 14.2. PLL Frequency Characteristics
45–80 MHz
30–60 MHz
25–50 MHz
19–30 MHz
SFR Definition 14.8. PLL0FLT: PLL Filter
5–8 MHz
R/W
Bit5
R/W
Bit4
PLLLP3
Rev. 1.4
Conditions
R/W
Bit3
C8051F120/1/2/3/4/5/6/7
PLLLP2
R/W
Bit2
PLLICO1-0
PLLLP3-0
0001
0011
0111
1111
00
01
10
11
C8051F130/1/2/3
PLLLP1
Min
25
5
R/W
Bit1
Typ
SFR Address:
PLLLP0 00110001
SFR Page:
R/W
Bit0
100*
Max
30
0x8F
F
Reset Value
Units
MHz
MHz
195