M3087BFLGP#U3 Renesas Electronics America, M3087BFLGP#U3 Datasheet - Page 191

• Manufacturer Part Number: M3087BFLGP#U3
• Description: IC M32C/87 MCU FLASH 144LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M32C/80r

Specifications of M3087BFLGP#U3

• Core Processor: M32C/80
• Core Size: 16/32-Bit
• Speed: 32MHz
• Connectivity: CAN, EBI/EMI, I²C, IEBus, IrDA, SIO, UART/USART
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 121
• Program Memory Size: 1MB (1M x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 34x10b, D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• For Use With: R0K330879S001BE - KIT DEV RSK M32C/87R0K330879S000BE - KIT DEV RSK M32C/87
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

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Chapter 4 Instruction Code
1 .
0
(4) Table of cycles
Content at start
Shows the number of cycles required to execute this instruction and the number of bytes in the instruc-
tion.
The number of cycles shown are the minimum possible, and they vary depending on the following conditions:
• Number of bytes that have been loaded in the instruction queue buffer
• Accessing of an external memory using 8-bit external bus
• Whether a wait is inserted in the bus cycle
Instruction bytes are indicated on the left side of the slash and execution cycles are indicated on the right side.
9
Contents at addresses following (start address of instruction + 2) are arranged as follows:
0 .
(1) Mnemonic
(2) Syntax
(3) Instruction code
B
Shows the mnemonic explained in this page.
Shows an instruction syntax using symbols.
Shows instruction code. Entered in ( ) are omitted depending on src/dest you selected.
address of
instruction
0
0
0000 0001 1 0 0 0 d4d3d2SIZEd1d0 1 1 1 1 1 1
b7
.size
3
.W
.B
1
2
Correspondence
9
0
0 -
0
6
SIZE
1
0 .
0
0
1
b0 b7
0
5
dsp16
abs16
#IMM16
abs24
dsp24
#IMM24
dsp8
#IMM8
3 .
1
address of instruc-
Content at (start
p
a
Rn
An
[An]
dsp:8[An]
g
e
tion+1)
b7
b7
b7
173
Low-order 8 bits
Low-order 8 bits
Correspondence
f o
dest
8 bits
3
R0L/R0/---
R1L/R1/---
R0H/R2/-
R1H/R3/-
A0
A1
[A0]
[A1]
dsp:8[A0]
dsp:8[A1]
3
+0
5
b0 b7
address of instruc-
Content at (start
b0
b0
b0
d4 d3 d2 d1 d0
1 0 0 1 0
1 0 0 1 1
1 0 0 0 0
1 0 0 0 1
0 0 0 1 0
0 0 0 1 1
0 0 0 0 0
0 0 0 0 1
0 0 1 0 0
0 0 1 0 1
tion+2)
b7
b7
High-order 8 bits
Middle-order 8bits
+1
Correspondence
dsp:8[SB/FB]
dsp:16[An]
dsp:16[SB/FB]
dsp:24[An]
abs16
abs24
b0
b0
b0
dest
(
b7
Contents at addresses following (start
dsp:8[SB]
dsp:8[FB]
dsp:16[A0]
dsp:16[A1]
dsp:16[SB]
dsp:16[FB]
dsp:24[A0]
dsp:24[A1]
abs16
abs24
High-order 8 bits
dsp8
dsp16/abs16
dsp24/abs24
address of instruction + 2)
(See the following figure.)
dest code
4.1
+2
d4 d3 d2 d1 d0
0 0 1 1 0
0 0 1 1 1
0 1 0 0 0
0 1 0 0 1
0 1 0 1 0
0 1 0 1 1
0 1 1 0 0
0 1 1 0 1
0 1 1 1 1
0 1 1 1 0
Guide to This Chapter
)
b0
#IMM8
#IMM16