MC9S12XDT256CAA Freescale Semiconductor, MC9S12XDT256CAA Datasheet - Page 722

• Manufacturer Part Number: MC9S12XDT256CAA
• Description: IC MCU 256K FLASH 80-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12XDT256CAA

• Core Processor: HCS12X
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 59
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.35 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-QFP
• Processor Series: S12XD
• Core: HCS12
• Data Bus Width: 16 bit
• Data Ram Size: 16 KB
• Interface Type: CAN/I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 59
• Number Of Timers: 12
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWHCS12
• Development Tools By Supplier: EVB9S12XDP512E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Chapter 19 S12X Debug (S12XDBGV2) Module
information (R/W, S/D etc.). The numerical suffix indicates which tracing step. The information format
for loop1 mode is the same as that of normal mode. Whilst tracing from XGATE or CPU only, in normal
or loop1 modes each array line contains data from entries made at 2 separate times, thus in this case the
DBGCNT[0] is incremented after each separate entry. In all other modes, DBGCNT[0] remains cleared
while the other DBGCNT bits are incremented on each trace buffer entry.
XGATE and S12X_CPU COFs occur independently of each other and the profile of COFs for the 2 sources
is totally different. When both sources are being traced in Normal or Loop1 mode, for each single entry
from one source, there may be many entries from the other source and vice versa, depending on user code.
COF events could occur far from each other in the time domain, on consecutive cycles or simultaneously.
If a COF occurs in one source only in a particular cycle, then the trace buffer bytes that are mapped to the
other source are redundant. Info byte bit CDV/XDV indicates that no useful information is stored in these
bytes. This is the typical case. Only in the rare event that both XGATE and S12X_CPU COF cycles
coincide is a valid trace buffer entry for both made, corresponding to the first line for mode "Both
Normal/Loop1" in
Single byte data accesses in detail mode are always stored to the low byte of the trace buffer (CDATAL or
XDATAL) and the high byte is cleared. When tracing word accesses, the byte at the lower address is always
stored to trace buffer byte3 and the byte at the higher address is stored to byte2
1
2
724
COF in CPU only. XGATE trace buffer entries in this tracing step are invalid
COF in XGATE only. CPU trace buffer entries in this tracing step are invalid
XGATE DETAIL
NORMAL
NORMAL
NORMAL
/ LOOP1
/ LOOP1
/ LOOP1
DETAIL
XGATE
Mode
CPU
CPU
Both
Table
CXINF1
CXINF2
CXINF1
CXINF2
1
2
CINF1
CINF3
XINF0
XINF1
XINF3
XINF1
XINF2
7
19-39.
CADRH1
CADRH2
CADRH1
CADRH2
CADRH1
CADRH3
6
Table 19-39. Trace Buffer Organization
MC9S12XDP512 Data Sheet, Rev. 2.21
CADRM1
CADRM2
CADRM1
CADRM2
CADRM1
CADRM3
XADRM0
XADRM2
XADRM1
XADRM3
5
8-Byte Wide Word Buffer
CADRL1
CADRL2
CADRL1
CADRL2
CADRL1
CADRL3
XADRL0
XADRL2
XADRL1
XADRL3
4
XDATAH1
XDATAH2
CDATAH1
CDATAH2
CINF0
CINF1
CINF2
CINF0
CINF2
XINF0
XINF2
3
XDATAL1
XDATAL2
CDATAL1
CDATAL2
CADRH0
CADRH1
CADRH0
CADRH2
2
Freescale Semiconductor
XADRM1
XADRM2
XADRM1
XADRM2
CADRM0
CADRM1
XADRM0
XADRM2
CADRM0
CADRM2
1
XADRL1
XADRL2
XADRL1
XADRL2
CADRL0
CADRL1
XADRL0
XADRL2
CADRL0
CADRL2
0