HD64F38024DV Renesas Electronics America, HD64F38024DV Datasheet - Page 310
![IC H8/SLP MCU FLASH 80QFP](/photos/12/20/122049/hd64f38024dv_sml.jpg)
HD64F38024DV
Manufacturer Part Number
HD64F38024DV
Description
IC H8/SLP MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300L SLPr
Datasheets
1.US38024-BAG1.pdf
(684 pages)
2.DF36012GFYV.pdf
(1021 pages)
3.DF38102HV.pdf
(145 pages)
Specifications of HD64F38024DV
Core Processor
H8/300L
Core Size
8-Bit
Speed
10MHz
Connectivity
SCI
Peripherals
LCD, PWM, WDT
Number Of I /o
51
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F38024DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 310 of 684
- Download datasheet (5Mb)
Section 9 Timers
Bit 5—Timer Overflow Interrupt Enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
0
1
Bit 4—Input Capture Interrupt Edge Select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
0
1
Bits 3 and 2—Counter Clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
0
0
1
1
Rev. 8.00 Mar. 09, 2010 Page 288 of 658
REJ09B0042-0800
Bit 2
CCLR0
0
1
0
1
Description
TCG overflow interrupt request is disabled
TCG overflow interrupt request is enabled
Description
Interrupt generated on rising edge of input capture input signal
Interrupt generated on falling edge of input capture input signal
Description
TCG clearing is disabled
TCG cleared by falling edge of input capture input signal
TCG cleared by rising edge of input capture input signal
TCG cleared by both edges of input capture input signal
(initial value)
(initial value)
(initial value)
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