C8051F022-GQ Silicon Laboratories Inc, C8051F022-GQ Datasheet - Page 200
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C8051F022-GQ
Manufacturer Part Number
C8051F022-GQ
Description
IC 8051 MCU 64K FLASH 100TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F02xr
Specifications of C8051F022-GQ
Program Memory Type
FLASH
Program Memory Size
64KB (64K x 8)
Package / Case
100-TQFP, 100-VQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
64
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F0x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SMBus/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
64
Number Of Timers
4
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F020DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 8-bit or 8-ch x 10-bit
On-chip Dac
2-ch x 12-bit
No. Of I/o's
64
Ram Memory Size
4352Byte
Cpu Speed
25MHz
No. Of Timers
5
Rohs Compliant
Yes
Cpu Family
C8051F02x
Device Core
8051
Device Core Size
8b
Frequency (max)
25MHz
Total Internal Ram Size
4.25KB
# I/os (max)
64
Number Of Timers - General Purpose
5
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Package Type
TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1200 - DEV KIT FOR F020/F021/F022/F023
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1202
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F022-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F022-GQ
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F022-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F020/1/2/3
Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when SPI0 is
configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the Mode Fault flag is set,
the MSTEN and SPIEN bits of the SPI control register are cleared by hardware, thereby placing the SPI0 module in
an "off-line" state. In a multiple-master environment, the system controller should check the state of the SLVSEL flag
(SPI0CN.2) to ensure the bus is free before setting the MSTEN bit and initiating a data transfer.
19.3. Serial Clock Timing
As shown in Figure 19.4, four combinations of serial clock phase and polarity can be selected using the clock control
bits in the SPI0 Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one of two clock phases
(edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-high or active-low clock. Both
master and slave devices must be configured to use the same clock phase and polarity. Note: SPI0 should be disabled
(by clearing the SPIEN bit, SPI0CN.0) while changing the clock phase and polarity.
The SPI0 Clock Rate Register (SPI0CKR) as shown in Figure 19.7 controls the master mode serial clock frequency.
This register is ignored when operating in slave mode.
200
SCK
(CKPOL=0, CKPHA=0)
SCK
(CKPOL=0, CKPHA=1)
SCK
(CKPOL=1, CKPHA=0)
SCK
(CKPOL=1, CKPHA=1)
MISO/MOSI
NSS
MSB
Figure 19.4. Data/Clock Timing Diagram
Bit 6
Bit 5
Rev. 1.4
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0