HD64F3644HV Renesas Electronics America, HD64F3644HV Datasheet - Page 457

• Manufacturer Part Number: HD64F3644HV
• Description: IC H8/3644 MCU FLASH 32K 64QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD64F3644HV

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-QFP
• Package: 64PQFP
• Family Name: H8
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 45
• Interface Type: SCI
• On-chip Adc: 8-chx8-bit
• Number Of Timers: 4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

A.3
The tables here can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table A.4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables as
follows:
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
From table A.4:
From table A.3:
Number of states required for execution = 2
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
From table A.4:
From table A.3:
Number of states required for execution = 2
BSET #0, @FF00
I = L = 2,
S
JSR @@ 30
I = 2,
S
I
I
= 2,
= S
Execution states = I
Number of Execution States
J
= S
J = K = 1,
S
K
L
= 2
= 2
J = K = M = N= 0
L = M = N = 0
S
I
+ J
S
J
+ K
2 + 2
2 + 1
S
K
+ L
2 = 8
2+ 1
Rev. 6.00 Sep 12, 2006 page 435 of 526
S
L
+ M
2 = 8
Appendix A CPU Instruction Set
S
M
+ N
S
N
REJ09B0326-0600