HD64F3644HV Renesas Electronics America, HD64F3644HV Datasheet - Page 351
HD64F3644HV
Manufacturer Part Number
HD64F3644HV
Description
IC H8/3644 MCU FLASH 32K 64QFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Lr
Datasheet
1.HD64F3644HV.pdf
(551 pages)
Specifications of HD64F3644HV
Core Processor
H8/300L
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
PWM, WDT
Number Of I /o
53
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
64-QFP
Package
64PQFP
Family Name
H8
Maximum Speed
8 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
45
Interface Type
SCI
On-chip Adc
8-chx8-bit
Number Of Timers
4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Notes: 1. When switching from transmission to simultaneous transmission/reception, check that
10.3.6
The multiprocessor communication function enables data to be exchanged among a number of
processors on a shared communication line. Serial data communication is performed in
asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the
transfer data).
In multiprocessor communication, each receiver is assigned its own ID code. The serial
communication cycle consists of two cycles, an ID transmission cycle in which the receiver is
specified, and a data transmission cycle in which the transfer data is sent to the specified receiver.
These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID
transmission cycle, and 0, a data transmission cycle.
The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver
it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the
transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it
compares the ID code with its own ID code, and if they are the same, receives the transfer data
sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor
bit set to 1 is sent again.
In this way, a number of processors can exchange data among themselves.
Figure 10.21 shows an example of communication between processors using the multiprocessor
format.
2. When switching from reception to simultaneous transmission/reception, check that
Multiprocessor Communication Function
SCI3 has finished transmitting and that bits TDRE and TEND are set to 1, clear bit TE
to 0, and then set bits TE and RE to 1 simultaneously with a single instruction.
SCI3 has finished receiving, clear bit RE to 0, then check that bit RDRF and the error
flags (OER, FER, and PER) are cleared to 0, and finally set bits TE and RE to 1
simultaneously with a single instruction.
Section 10 Serial Communication Interface
Rev. 6.00 Sep 12, 2006 page 329 of 526
REJ09B0326-0600
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