MC908GP32CPE Freescale Semiconductor, MC908GP32CPE Datasheet - Page 63

• Manufacturer Part Number: MC908GP32CPE
• Description: IC MCU 8MHZ 32K FLASH 40-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908GP32CPE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 33
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Processor Series: HC08GP
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68CBL05CE, M68EML08GPGTE
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

5.3.1 Crystal Oscillator Circuit
The crystal oscillator circuit consists of an inverting amplifier and an external crystal. The OSC1 pin is the
input to the amplifier and the OSC2 pin is the output. The SIMOSCEN signal from the system integration
module (SIM) or the OSCSTOPENB bit in the CONFIG register enable the crystal oscillator circuit.
The CGMXCLK signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal
frequency. CGMXCLK is then buffered to produce CGMRCLK, the PLL reference clock.
CGMXCLK can be used by other modules which require precise timing for operation. The duty cycle of
CGMXCLK is not guaranteed to be 50% and depends on external factors, including the crystal and related
external components. An externally generated clock also can feed the OSC1 pin of the crystal oscillator
circuit. Connect the external clock to the OSC1 pin and let the OSC2 pin float.
5.3.2 Phase-Locked Loop Circuit (PLL)
The PLL is a frequency generator that can operate in either acquisition mode or tracking mode, depending
on the accuracy of the output frequency. The PLL can change between acquisition and tracking modes
either automatically or manually.
5.3.3 PLL Circuits
The PLL consists of these circuits:
The operating range of the VCO is programmable for a wide range of frequencies and for maximum
immunity to external noise, including supply and CGMXFC noise. The VCO frequency is bound to a range
from roughly one-half to twice the center-of-range frequency, f
CGM/XFC pin changes the frequency within this range. By design, f
center-of-range frequency, f
(L × 2
CGMRCLK is the PLL reference clock, a buffered version of CGMXCLK. CGMRCLK runs at a frequency,
f
factor, R. The divider’s output is the final reference clock, CGMRDV, running at a frequency,
f
With an external high-frequency clock source, use R to divide the external frequency to between 30 kHz
and 100 kHz.
The VCO’s output clock, CGMVCLK, running at a frequency, f
prescale divider and a programmable modulo divider. The prescaler divides the VCO clock by a
power-of-two factor P and the modulo divider reduces the VCO clock by a factor, N. The dividers’ output
is the VCO feedback clock, CGMVDV, running at a frequency, f
Programming the PLL
Freescale Semiconductor
RCLK
RDV
•
•
•
•
•
•
•
= f
, and is fed to the PLL through a programmable modulo reference divider, which divides f
E
Voltage-controlled oscillator (VCO)
Reference divider
Frequency prescaler
Modulo VCO frequency divider
Phase detector
Loop filter
Lock detector
)f
RCLK
NOM
.
/R. With an external crystal (30 kHz–100 kHz), always set R = 1 for specified performance.
for more information.)
NOM
, (38.4 kHz) times a linear factor, L, and a power-of-two factor, E, or
MC68HC908GP32 Data Sheet, Rev. 10
VCLK
VRS
VDV
. Modulating the voltage on the
, is fed back through a programmable
VRS
= f
VCLK
is equal to the nominal
/(N × 2
P
). (See
Functional Description
5.3.6
RCLK
by a
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