HD64F3687GFPV Renesas Electronics America, HD64F3687GFPV Datasheet - Page 210

• Manufacturer Part Number: HD64F3687GFPV
• Description: IC H8 MCU FLASH 56K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300H Tinyr

Specifications of HD64F3687GFPV

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, SCI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 45
• Program Memory Size: 56KB (56K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 64-LQFP
• Package: 64LQFP
• Family Name: H8
• Maximum Speed: 20 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16|32 Bit
• Number Of Programmable I/os: 45
• Interface Type: I2C/SCI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 3
• For Use With: R0K436079S000BE - KIT DEV FOR H8/36079 W/COMPILER
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 13 Timer Z
Table 13.1 Timer Z Functions
Rev.5.00 Nov. 02, 2005 Page 176 of 500
REJ09B0027-0500
Item
Count clock
General registers
(output compare/input
capture registers)
Buffer register
I/O pins
Counter clearing function
Compare
match output
Input capture function
Synchronous operation
PWM mode
Reset synchronous PWM
mode
Complementary PWM
mode
Buffer function
Interrupt sources
Eleven interrupt sources
Four compare match/input capture interrupts and an overflow interrupt are available for
each channel. An underflow interrupt can be set for channel 1.
0 output
1 output
output
Channel 0
Internal clocks: , /2, /4, /8
External clock: FTIOA0 (TCLK)
GRA_0, GRB_0, GRC_0, GRD_0 GRA_1, GRB_1, GRC_1, GRD_1
GRC_0, GRD_0
FTIOA0, FTIOB0, FTIOC0,
FTIOD0
Compare match/input capture of
GRA_0, GRB_0, GRC_0, or
GRD_0
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compare match/input capture A0
to D0
Overflow
Channel 1
GRC_1, GRD_1
FTIOA1, FTIOB1, FTIOC1,
FTIOD1
Compare match/input capture of
GRA_1, GRB_1, GRC_1, or
GRD_1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Compare match/input capture A1
to D1
Overflow
Underflow