DSP56F801FA80E Freescale Semiconductor, DSP56F801FA80E Datasheet - Page 3

• Manufacturer Part Number: DSP56F801FA80E
• Description: IC DSP 80MHZ 8K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxr

Specifications of DSP56F801FA80E

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 80MHz
• Connectivity: SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 11
• Program Memory Size: 20KB (10K x 16)
• Program Memory Type: FLASH
• Ram Size: 2K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Package: 48LQFP
• Family Name: 56F8xx
• Maximum Speed: 80 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 11
• Interface Type: SCI/SPI
• On-chip Adc: 2(4-chx12-bit)
• Number Of Timers: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

56F801 General Description
Freescale Semiconductor
• Up to 30 MIPS operation at 60MHz core frequency
• Up to 40 MIPS operation at 80MHz core frequency
• DSP and MCU functionality in a unified,
• MCU-friendly instruction set supports both DSP and
• Hardware DO and REP loops
• 6-channel PWM Module
• Two 4-channel, 12-bit ADCs
• Serial Communications Interface (SCI)
• Serial Peripheral Interface (SPI)
C-efficient architecture
controller functions: MAC, bit manipulation unit, 14
addressing modes
4
4
3
2
4
6
*
A/D1
A/D2
PWM Outputs
Quad Timer C
VREF
Quad Timer D
Fault Input
includes TCS pin which is reserved for factory use and is tied to VSS
or GPIO
GPIO
GPIO
SCI0
SPI
or
or
ADC
tion-Specific
Peripherals
Program Memory
1024 x 16 SRAM
1024 x 16 SRAM
Memory &
8188 x 16 Flash
2048 x 16 Flash
2048 x 16 Flash
Applica-
Data Memory
Boot Flash
Watchdog
Controller
PWMA
Interrupt
COP/
RESET
Hardware Looping Unit
•
MODULE CONTROLS
ADDRESS BUS [8:0]
Program Controller
DATA BUS [15:0]
IRQA
•
COP RESET
56F801 Technical Data, Rev. 17
56F801 Block Diagram
•
and
XAB1
XAB2
XDB2
CGDB
PAB
PDB
INTERRUPT
CONTROLS
6
JTAG/
OnCE
Port
Generation
•
Address
Unit
•
IPBus Bridge
16
•
• 8K × 16-bit words (16KB) Program Flash
• 1K × 16-bit words (2KB) Program RAM
• 2K × 16-bit words (4KB) Data Flash
• 1K × 16-bit words (2KB) Data RAM
• 2K × 16-bit words (4KB) Boot Flash
• General Purpose Quad Timer
• JTAG/OnCE
• On-chip relaxation oscillator
• 11 shared GPIO
• 48-pin LQFP Package
(IPBB)
•
CONTROLS
VCAPC V
2
IPBB
Three 16-bit Input Registers
16 x 16 + 36 → 36-Bit MAC
Two 36-bit Accumulators
4
16
Digital Reg
•
DD
Data ALU
TM
16-Bit
56800
5*
V
Low Voltage
Core
Supervisor
SS
port for debugging
V
DDA
Analog Reg
Relaxation Osc.
Manipulation
or Optional
Clock Gen
V
Internal
SSA
PLL
Unit
Bit
GPIOB3/XTAL
GPIOB2/EXTAL
3