R5F21237DFP#U0 Renesas Electronics America, R5F21237DFP#U0 Datasheet - Page 367
![IC R8C/23 MCU FLASH 48-LQFP](/photos/12/18/121887/r5f21237dfp_u0_sml.jpg)
R5F21237DFP#U0
Manufacturer Part Number
R5F21237DFP#U0
Description
IC R8C/23 MCU FLASH 48-LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Specifications of R5F21237DFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0K521237S000BE - KIT DEV RSK R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.41
16.3.4
16.3.4.1
When setting the FS bit in the SAR register to 1, the clock synchronous serial format is used to communicate.
Figure 16.41 shows the Transfer Format of Clock Synchronous Serial Format.
When the MST bit in the ICCR1 register is set to 1, the transfer clock is output from the SCL pin and when the
MST bit is set to 0, the external clock is input.
The transfer data is output between the fall and the following fall of the SCL clock, and data is determined by
the rise of the SCL clock. The MSB-first or LSB-first can be selected for the order of the data transfer by setting
the MLS bit in the ICMR register. The SDA output level can be changed by the SDAO bit in the ICCR2 register
during the transfer standby.
Clock Synchronous Serial Mode
SCL
SDA
Clock Synchronous Serial Format
Transfer Format of Clock Synchronous Serial Format
Page 345 of 501
b0
b1
b2
b3
b4
b5
16. Clock Synchronous Serial Interface
b6
b7
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